3 Commits

Author	SHA1	Message	Date
Jagan Teki	8606f960d4	clk: sunxi: Implement UART resets ... Implement UART resets for all relevant Allwinner SoC clock drivers via ccu reset table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>	2019-01-18 22:19:09 +05:30
Jagan Teki	4acc711930	clk: sunxi: Implement UART clocks ... Implement UART clocks for all Allwinner SoC clock drivers via ccu clock gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>	2019-01-18 22:19:09 +05:30
Jagan Teki	6239a6d092	clk: sunxi: Add Allwinner V3S CLK driver ... Add initial clock driver for Allwinner V3S. - Implement USB bus and USB clocks via ccu_clk_gate table for V3S, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for V3S, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>	2019-01-18 22:19:09 +05:30