Xilfpga library expects the size of bitstream in a pointer
but currenly we are passing the size as a value. This patch
fixes this issue.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Latest xilfpga expects to set BIT5 of flags for nonsecure
bitsream and also expects length in bytes instead of words
This patch does the same.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds support for ZynqMP platform to print FPGA PCAP status
for "fpga status" command.
Signed-off-by: Nitin Jain <nitinj@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
As we aren't quite able to convert some platforms with a very small size
limit in SPL yet, we need to revert this for now.
This reverts commit 7b09477873.
Signed-off-by: Tom Rini <trini@konsulko.com>
As we aren't quite able to convert some platforms with a very small size
limit in SPL yet, we need to revert this for now.
This reverts commit 37434db29b.
Signed-off-by: Tom Rini <trini@konsulko.com>
A debug string still has the old name of a function being called; update
it.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fix Kconfig alignment which should be <tab><space><space>.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As of commit 1a1fa24066 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the rx8025 implementation of
rtc_reset() does not need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
As of commit 1a1fa24066 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the rs5c372 implementation of
rtc_reset() does not need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
As of commit 1a1fa24066 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the mx27rtc implementation of
rtc_reset() can be an empty stub function.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
As of commit 1a1fa24066 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the ds1374 implementation of
rtc_reset() doesn't need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
As of commit 1a1fa24066 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the ds1307 implementation of
rtc_reset() doesn't need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The STGEN is the clock source for the Cortex A7 arch timer.
So after modification of its frequency, CP15 cntfreq is updated
and a new timer init is performed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Adds devicemodel support to the ISL1208 driver.
This patch drops the non-dm API as no board was using it anyway.
Also add it to Kconfig.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We should not evaluate the value of reg before its value is set.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
include/commproc.h is dedicated to the 8xx, rename it cpm_8xx.h and
move it into arch/powerpc/include/asm
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
CONFIG_8xx doesn't mean much outside of arch/powerpc/
This patch renames it CONFIG_MPC8xx just like CONFIG_MPC85xx etc ...
It also renames 8xx_immap.h to immap_8xx.h to be consistent with
other file names.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
commit 907208c452 ("powerpc: Partialy restore core of mpc8xx")
didn't bring back support for I2C on the mpc8xx
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
ATMEL_SPI is now fully converted to driver-model and
respective boards switch to DM_SPI as well,
so make default y for ARCH_AT91
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
atmel_spi.h has register offsets, and atmel_spi_slave
structure, move it into .c file for better readability
and drop atmel_spi.h
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
All board configs are now enabled DM_SPI for SPL and
U-Boot proper, so now its time to drop non-dm code.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
Few boards are configuring gpio directly from board instead
using drivers/gpio so add ifdef for DM_GPIO to compatible
for both the cases.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
Highlights this time around:
- Support for new RPi3 B+ model
- Fix for some SD cards on newer RPi firmware
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Merge tag 'signed-rpi-next' of git://github.com/agraf/u-boot
Patch queue for rpi - 2018-04-06
Highlights this time around:
- Support for new RPi3 B+ model
- Fix for some SD cards on newer RPi firmware
In raspberrypi-firmware 7fdcd00e00a42a1c91e8bd6f5eb8352fe9358557 and
later start.elf now sets the EMMC clock to 200 MHz.
According to Phil Elwell in
https://github.com/raspberrypi/firmware/issues/953
the SDHost controller shares the core/VPU clock and doesn't use
the EMMC clock.
Use the core clock id when determining the frequency to allow
U-Boot to work with recent versions of raspberrypi-firmware.
Otherwise U-Boot hangs at:
U-Boot 2018.03 (Mar 14 2018 - 20:36:00 +1100)
DRAM: 948 MiB
RPI 3 Model B (0xa02082)
MMC: mmc@7e202000: 0, sdhci@7e300000: 1
Loading Environment from FAT...
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
In January some commits were introduced to mitigate the U-Boot image
size issues we encountered on sunxi builds.
Now with the MMC environment removed we can bring them back, as we
practically don't have a size limit anymore.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The original DT binding used by U-Boot's sun8i-emac driver was not really
agreed upon, and deviated from the "official" binding now used by the
kernel. Since now all U-Boot users have been converted to the new
binding, we can remove support for the old DT nodes from the driver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an
upstream Linux driver in v4.15.
This one uses a slightly different binding from the original one used
by the U-Boot driver.
The differences to the old binding are:
- The "syscon" address is held in a separate node, referenced via a
phandle in the "syscon" property.
- The reference to the PHY is held in a property called "phy-handle",
not "phy".
- The PHY register is at offset 0x30 in the syscon device, not at 0.
- The internal PHY is activated when the node, which phy-handle points
to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node.
Teach the U-Boot driver how to find its resources in a "new-style" DT,
so that we can use a Linux kernel compatible DT for U-Boot as well.
This keeps support for the old binding for now, to allow a smooth
transition.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The Linux kernel driver for the Allwinner pin controller gained support
for generic properties, which are now also used in the DTs.
The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from
the DT, but so far only supported the old binding.
Update the parsing routine to cope with both the old and new bindings,
so that the newer DTs can be used with U-Boot and its Ethernet driver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The sunxi GPIO driver is missing some compatible strings for recent
SoCs. While most of the sunxi GPIO code seems to not rely on this (and
so works anyway), the sunxi_name_to_gpio() function does and fails at
the moment (for instance when resolving the MMC CD pin name).
Add the compatible strings for the A64 and V3s, which were missing
from the list. This now covers all pinctrl nodes in our own DTs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Move the NAND parameters from defconfig files to Kconfig for SUNXI
architecture only. Fort now only the CHIP pro is migrated.
It would have been better to convert this defconfig entry to Kconfig for
all supported machines/architectures but it has been abandoned due to a
fairly high amount of errors reported by the moveconfig.py tool. This is
due to defines quite often being multiplications of values/other defines
not correctly handled.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Remove NAND_SUNXI from the CHIP pro defconfig to be automatically
selected depending on the state of ARCH_SUNXI.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Make SUNXI_NAND select SPL_NAND_SUPPORT in Kconfig, this limit the
number of entries to add in defconfig files when adding NAND support.
For now, the only board using it is the CHIP pro.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I
in Kconfig.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
SPL support was first written to support only the earlier generations of
Allwinner SoCs, and was only really enabled on the A13 / GR8. However,
those old SoCs had a DMA engine that has been replaced since the A31 by
another DMA controller that is no longer compatible.
Since the code directly uses that DMA controller, it cannot operate
properly on the later SoCs, while the NAND controller has not changed.
There's two paths forward, the first one would have been to add support
for that DMA controller too, the second to just remove the DMA usage
entirely and rely on PIO.
The later has been chosen because CPU overload at this stage is not an
issue and it makes the driver more generic, and easier to understand.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Move the ecc_bytes array out of nand_max_ecc_strength() for future use
by nand_read_page().
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Prepare the future use of an helper to move the data pointer (the
column) of the NAND chip by renaming nand_reset_column() to
nand_change_column(). Resetting the column is just a matter of giving 0
as argument.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
When changing the column, the ONFI specification states that a minimum
time of tCCS (Change Column Setup time) must elapse between the last
address cycle is asserted on the bus and the first data cycle is
clocked. An usual value for average NANDs is 500 nanoseconds. Round it
up to 1 microsecond to be safe.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Executing a command is matter of always doing the following sequence:
* Waiting for the FIFO to be empty so we can fill it with the new
command.
* Clearing the status register.
* Writing the command in the FIFO.
* Waiting for the command to finish.
Add a nand_exec_cmd() helper to handle this instead of repeating the
logic through the various functions.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
It is best practice to always clear the status register before executing
a command to be sure that the status read afterwards is relevant.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
One bit in the control registers indicates if the NAND controller is
ready to receive a new command. Otherwise, the command FIFO is full and
we should wait for this bit to flip. It then states that the last
command has been processed and the FIFO is now free to welcome another
command.
Add this sanity check before starting any new command.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The pattern of polling on a status register until a bit is set or a
timeout occurs is repeated multiple times in the driver. Mutualize the
code by introducing the nand_wait_int() helper that does wait for the
bit to flip or returns an error in case of timeout.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
