Commit Graph

18903 Commits

Author SHA1 Message Date
Bin Meng
7365a03804 pci: fsl_pci_init: Dynamically allocate the PCI regions
Commit e002474158 ("pci: pci-uclass: Dynamically allocate the PCI regions")
changes 'struct pci_controller'.regions from pre-allocated array of
regions to dynamically allocated, which unfortunately broken lots of
boards that still use the non-DM PCI driver.

This patch changes the non-DM fsl_pci_init driver to dynamically
allocate the regions, just like what's done in the pci uclass driver.

Fixes: e002474158 ("pci: pci-uclass: Dynamically allocate the PCI regions")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-05 10:25:42 +05:30
Bin Meng
384b62c073 serial: ns16550: Handle zero <clock-frequency> value
A working device tree node of ns16550 should never be populated
with value zero for the <clock-frequency> property. Unfortunately
this is the case for the QEMU ppce500 target.

Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the
last resort to handle such case.

This commit should be reverted when:

- The following QEMU patch [1] is merged, and
- U-Boot CI has upgraded its QEMU version that contains the fix

[1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-03 19:17:25 -07:00
Bin Meng
09bd08401a serial: ns16550: Correct the base address type
Currently ns16550_serial_assign_base() treats the argument 'base'
with type `ulong`. This is incorrect because the base address was
obtained from device tree with type `fdt_addr_t` that can represent
a physical address larger than 32-bit in a 32-bit system.

Fixes: 9e6ce62190 ("serial: ns16550: Fix ordering of getting base address")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-03 19:17:25 -07:00
Heinrich Schuchardt
297b8b3ebf sandbox: host bind must close file descriptor
Each invocation of the 'host bind' command with a file name argument opens
a file descriptor. The next invocation of the 'host bind' command destroys
the block device but the file descriptor remains open. The same holds true
for the 'unbind blk' command.

Close the file descriptor when unbinding the host block device.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-03 19:17:25 -07:00
Simon Glass
15421b71bc dm: core: Add DM_DEVICE_REMOVE condition to all exit paths
At present device_bind() does some unnecessary work if a device fails to
bind in SPL. Add the missing conditions.

Also fix a style nit in the same function while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-03 19:17:25 -07:00
Simon Glass
24fd7e383d dm: core: Fix allocation of empty of-platdata
With of-platdata we always have a dtv struct that holds the platform data
provided by the driver_info record. However, this struct can be empty if
there are no actual devicetree properties provided.

The upshot of empty platform data is that it will end up as a zero-size
member in the BSS section, which is fine. But if the driver specifies
plat_auto then it expects the correct amount of space to be allocated.

At present this does not happen, since device_bind() assumes that the
platform-data size will always be >0. As a result we end up not
allocating the space and just use the BSS region, overwriting whatever
other contents are present.

Fix this by removing the condition that platform data be non-empty, always
allocating space if requested.

This fixes a strange bug that has been lurking since of-platdata was
implemented. It has likely never been noticed since devices normally have
at least some devicetree properties, BSS is seldom used on SPL, the dtv
structs are normally at the end of bss and the overwriting only happens
if a driver changes its platform data.

It was discovered using sandbox_spl, which exercises more features than
a normal board might, and the critical global_data variable 'gd' happened
to be at the end of BSS.

Fixes: 9fa2819009 ("dm: core: Expand platdata for of-platdata devices")
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-03 19:17:25 -07:00
Tom Rini
52ba373b78 i.MX for 2021.04
----------------
 
 - new boards:
 	- i.MX8MN Beacon EmbeddedWorks (2GB)
 	- Gateworks Venice imx8mm
 - convert to DM:
 	- imx53-qsb, mx53loco, mx51evk, mx23-evk
 - Fixes :
 	- Network : FEC ethernet quirks
 	- DH dh-imx6
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6597
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Merge tag 'u-boot-imx-20210303' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX for 2021.04
----------------

- new boards:
	- i.MX8MN Beacon EmbeddedWorks (2GB)
	- Gateworks Venice imx8mm
- convert to DM:
	- imx53-qsb, mx53loco, mx51evk, mx23-evk
- Fixes :
	- Network : FEC ethernet quirks
	- DH dh-imx6

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6597
2021-03-03 10:10:34 -05:00
Heinrich Schuchardt
795d605cab usb: USB keyboard requires DM_KEYBOARD
If CONFIG_DM_USB=y, the USB keyboard only works if CONFIG_DM_KEYBOARD=y.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-03-03 04:12:46 +01:00
Pali Rohár
7f98575b7b usb: gadget: Use dbg_ep0() macro instead of serial_printf()
All debug messages from ep0.c except a few are printed by dbg_ep0() macro.
So for remaining few exceptions use also dbg_ep0() instead of serial_printf().

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:46 +01:00
Pali Rohár
f2e81c1d38 usb: musb: Ensure that we set musb dynamic FIFO buffer for every endpoint
If we do not set FIFO buffer address and size for some endpoint which is in
use then default programmed address 0x0 would be used which is in conflict
with address of FIFO buffer for endpoint 0. Moreover address of FIFO buffer
for endpoint 0 cannot be programmed, it is fixed to 0x0. Sharing address
space between more endpoints cause data loss and unexpected errors.

This patch is fixing transmission of characters over usbtty serial console
and allows using of usbtty for debugging purposes on Nokia N900.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:46 +01:00
Pali Rohár
f1e8d2072c usb: musb: Fix handling interrupts for EP0 and SET ADDRESS commmand
Interrupt for EP0 is indicated in intrtx register via first bit. This bit
is set for both RX and TX despite register has only TX in its name. First
bit in intrrx register is reserved, not used and never set.

So remove calling musb_peri_ep0() function at every iteration of udc_irq()
and musb_peri_rx() and call it only from musb_peri_tx() when correct
interrupt bit in initrtx it set.

Address from SET ADDRESS command must be set to faddr register only after
acknowledging SERV_RXPKTRDY followed by received EP0 interrupt. So prior
calling musb_peri_ep0_set_address() check for EP0 interrupt instead of
(incorrect) MUSB_INTR_SOF interrupt.

This patch fixes issue that host (computer) cannot register U-Boot USB
device and is failing with errors:

    usb 1-1: new full-speed USB device number 86 using xhci_hcd
    usb 1-1: Device not responding to setup address.
    usb 1-1: Device not responding to setup address.
    usb 1-1: device not accepting address 86, error -71

U-Boot was writing address to faddr register too early and did not wait for
correct interrupt after which should update address.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:46 +01:00
Pali Rohár
ff77bb301e usb: musb: Fix receiving of bigger buffers
If musb_peri_rx_ep() was called to process received HW buffer but U-Boot
cannot read it yet (e.g. because U-Boot SW buffer is full) then interrupt
was marked as processed also when HW buffer stayed unprocessed.

U-Boot tried to process this buffer again when it received interrupt again,
but it can receive it only when sender (host) sends a new data. As sender
(host) is not going to send a new data until U-Boot process current data
this issue caused a deadlock in case sender (host) is emitting data faster
than U-Boot can process it.

Reading musb intrrx register automatically clears this register and marks
interrupt as processed. So to prevent marking interrupt in U-Boot as
processed, adds a new variable pending_intrrx which would contain
unprocessed bits of intrrx register.

For a second step, every time when musb_peri_rx_ep() is called and there
are waiting data to be processed (signaled by MUSB_RXCSR_RXPKTRDY) either
acknowledge sender (via musb_peri_rx_ack()) that whole HW buffer was
processed or set corresponding bit in pending_intrrx that HW buffer was not
fully processed yet and next iteration is required after U-Boot allocates
space for reading HW buffer.

This patch fixes receiving large usb buffers, e.g. file transfer via Kermit
protocol implemented by 'loadb' U-Boot command over usbtty serial console.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:46 +01:00
Pali Rohár
ea7125c4c6 usb: musb: Fix transmission of bigger buffers
If udc_endpoint_write() was called with bigger payload which does not fit
into one USB packet it is needed to transmit payload in more USB packets.
First packet is transmitted by udc_endpoint_write() call itself and other
packets are put into waiting queue.

Implement function musb_peri_tx() which checks if endpoints are ready for
transmit and continue transmission of waiting queue.

This patch fixes sending big output from printenv command over usbtty
serial console.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>>
2021-03-03 04:12:46 +01:00
Pali Rohár
7d7ae28c8b usb: musb: Read value of PERI_RXCSR to 16bit variable
PERI_RXCSR is 16bit register so store its value into 16bit local variable.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:46 +01:00
Pali Rohár
10bc132510 usb: musb: Fix configuring FIFO for endpoints
This patch fixes configuring FIFOs for one-directional endpoints which have
only one queue (either RX or TX, but noth both).

Size of FIFO buffer is 2^(idx+3) bytes and starting address is 2^(addr+3).
Moreover first 64 bytes are reserved for EP0.

Without this patch if FIFO size specified by caller was zero then idx was
incorrectly calculated (expr. ffs(0)-1) and size overflowed in fifosz
register. This register uses has only 4 bits for FIFO size. Moreover
specifying zero buffer size is not possible (with idx=0 is minimal buffer
size 8 bytes).

So even for one-directional endpoints we need to correctly specify both
(RX and TX) FIFO buffer sizes and its addresses.

This patch is fixing calculation of start address and buffer size to
minimal value and ensures that it would not overlap with buffer reserved
for EP0.

This issue caused loose of packets on USB bus in both directions and
basically usbtty was unusable.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:46 +01:00
Pali Rohár
a6f5e1b9cd usb: musb: Always clear the data toggle bit when configuring ep
Without this patch clearing was done only when U-Boot was compiled with
MUSB Host Controller. But clearing of data toggle bit is needed also for
MUSB Device Controller otherwise Device Controller does not work correctly.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:45 +01:00
Pali Rohár
7f840c1b26 serial: usbtty: Send urb data in correct order
Function next_urb() selects the last urb data buffer from linked list to
which next data from usbtty's puts function should be appended.

But to check if TX data still exists it is needed to look at the first urb
data buffer from linked list. So check for endpoint->tx_urb (first from the
linked list) instead of current_urb (the last from the linked list).

Successful call to udc_endpoint_write() may invalidate active urb and
allocate new urb in queue which invalidates pointer returned by next_urb()
function.

So call next_urb() prior putting data into urb buffer and call it every
time after using udc_endpoint_write() function to prevent sending data from
usbtty's puts function in incorrect order.

This patch fixes issue that usbtty code does not transmit data when they
are waiting in the tx queue.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:45 +01:00
Pali Rohár
d3fb8fee7d serial: usbtty: Fix puts function
This function has incorrect implementation of prepending CR prior LF.
Without this patch it prepended CR prior whole string which is going to be
written and let LF without leading CR. Fix this issue by inserting CR at
correct place to make output on usbtty serial console more readable.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
2021-03-03 04:12:45 +01:00
Matthias Brugger
3ac05239b4 rng: iproc_rng200: Enable support for RPi4 armv7
On the RPi4 armv7 build we have the situationt that we use physical
addresses of 64 bit, while the virtual addresses are 32 bit.
Remap the base address in this scenario via map_physmem().

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-03-02 13:53:48 +01:00
Bharat Gooty
76cffd5795 drivers: mmc: iproc_sdhci: enable HS200 mode
Add tuning functionality which is needed for HS200 mode.
For HS200, program the correct needed 1.8 voltage

Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-03-02 13:53:37 +01:00
Haibo Chen
0ba116a319 mmc: fsl_esdhc_imx: fix the DTOCV to 0xE
On imx6Q/imx6DL, we find if config the DTOCV to 0~3, it will impact
cmd6 behavior, after cmd6 get transfer complete interrupt, the data0
line will keep low over 5 seconds. This should be a IC bug on imx6Q/DL.
For other platforms, do not has this issue.

To fix this issue, fix the DTOCV to 0xE, the max setting, this also align
with Linux configuration.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-03-01 10:21:36 +01:00
Fabio Estevam
c3e6f99e73 mmc: fsl_esdhc_imx: Add a compatible for i.MX51
Add a compatible for i.MX51 so that i.MX51 can use this driver
via driver model.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-03-01 10:21:36 +01:00
Tim Harvey
deb78ff34e thermal: imx_tmu: enable monitoring and default alert/critical
Set default critical/alert temperature and enabling monoitoring.

Without calling imx_tmu_enable_msite() monitoring will not be enabled
and read_temperature will return 0. Additionally without setting alert
temperature will cause imx_tmu_get_temp() to spin indefiniately thinking
the system needs to cool.

This resolves the board spinning endlessly when enabling IMX_TMU in the
SPL.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-03-01 10:21:36 +01:00
Tom Rini
08cca188c1 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb
- fastboot updates / fixes
2021-02-26 15:11:08 -05:00
Tom Rini
b839fc9d47 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- new GigaDevice flash ids
- fixes for imx, nxp_spi drivers
2021-02-26 12:41:19 -05:00
Patrice Chotard
0a7e5e5f10 usb: gadget: dwc2_udc_otg: Fix dwc2_gadget_start() and usb_gadget_register_driver()
Since commit 8745b9ebcc ("usb: gadget: add super speed support")
ums was no more functional on platform which use dwc2_udc_otg driver.

This was due to a too restrictive test which checked that the gadget
driver speed was either FS or HS.

So all gadget driver with max speed set to speed higher than
HS (SS in case of composite gadget driver in our case) are not
allowed, which is wrong.

Update the speed test in usb_gadget_register_driver() and in
dwc2_gadget_start() to allow all gadget driver speed equal or higher
than FS.

Tested on stm32mp157c-ev1 board.

Fixes: c791c8431c ("usb: dwc2: convert driver to DM_USB_GADGET")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-02-26 15:30:55 +01:00
Heiko Schocher
bc820d5bcc fastboot: add UUU command UCmd and ACmd support
add support for the UUU commands ACmd and UCmd.

Enable them through the Kconfig option
CONFIG_FASTBOOT_UUU_SUPPORT

base was commit in NXP kernel
9b149c2a2882: ("MLK-18591-3 android: Add FSL android fastboot support")

and ported it to current mainline. Tested this patch
on imx6ul based board.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-02-26 15:30:55 +01:00
Sean Anderson
de1728ce4c fastboot: Allow u-boot-style partitions
This adds support for partitions of the form "dev.hwpart:part" and
"dev#partname". This allows one to flash to eMMC boot partitions without
having to use CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT. It also allows one to
flash to an entire device without needing CONFIG_FASTBOOT_MMC_USER_NAME.
Lastly, one can also flash MMC devices other than
CONFIG_FASTBOOT_FLASH_MMC_DEV.

Because devices can be specified explicitly, CONFIG_FASTBOOT_FLASH_MMC_DEV
is used only when necessary for existing functionality. For those cases,
fastboot_mmc_get_dev has been added as a helper function. This allows

There should be no conflicts with the existing system, but just in case, I
have ordered detection of these names after all existing names.

The fastboot_mmc_part test has been updated for these new names.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
ae5e6b4e8f fastboot: Move part_get_info_by_name_or_alias after raw_part_get_info_by_name
This makes the next commit more readable by doing the move now.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
f3cf964f2d fastboot: Remove mmcpart argument from raw_part_get_info_by_name
The only thing mmcpart was used for was to pass to blk_dselect_hwpart.
This calls blk_dselect_hwpart directly from raw_part_get_info_by_name. The
error handling is dropped, but it is reintroduced in the next commit
(albeit less specificly).

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
3f6fb77175 mmc: sandbox: Add support for writing
This adds support writing to the sandbox mmc backed by an in-memory
buffer. The unit test has been updated to test reading, writing, and
erasing. I'm not sure what MMCs erase to; I picked 0, but if it's 0xFF
then that can be easily changed.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Tom Rini
99bebbd5b2 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- turris_mox: Enhancements, mostlly defconfig changes (Pali)
- pci-aardvark: Set Max Payload Size and Max Read Request Size
                to 512 bytes (Pali)
- pci_mvebu: Minor cleanup and refactoring (Marek)
- Upgrade A38x DDR3 training to version 14.0.0 (Marek)
2021-02-26 07:55:16 -05:00
Tom Rini
d9bc92f554 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsung 2021-02-26 07:54:27 -05:00
Reto Schneider
783a15b351 mtd: nand: spi: Support GigaDevice GD5F1GQ5UExxG
The relevant changes to the already existing GD5F1GQ4UExxG support has
been determined by consulting the GigaDevice product change notice
AN-0392-10, version 1.0 from November 30, 2020.

As the overlaps are huge, variable names have been generalized
accordingly.

Apart form the lowered ECC strength (4 instead of 8 bits per 512 bytes),
the new device ID, and the extra quad IO dummy byte, no changes had to
be taken into account.

New hardware features are not supported, namely:
 - Power on reset
 - Unique ID
 - Double transfer rate (DTR)
 - Parameter page
 - Random data quad IO

The inverted semantic of the "driver strength" register bits, defaulting
to 100% instead of 50% for the Q5 devices, got ignored as the driver has
never touched them anyway.

The no longer supported "read from cache during block erase"
functionality is not reflected as the current SPI NAND core does not
support it anyway.

Implementation has been tested on MediaTek MT7688 based GARDENA smart
Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 16:01:37 +05:30
Hauke Mehrtens
12926f46fd mtd: nand: spi: Only one dummy byte in QUADIO
The datasheet only lists one dummy byte in the 0xEB operation for the
following chips:
* GD5F1GQ4xExxG
* GD5F1GQ4xFxxG
* GD5F1GQ4UAYIG
* GD5F4GQ4UAYIG

Reto Schneider:
- Linux patch ported to U-Boot
- Checked for compatibility with GD5F1GQ4xBxxG
- Fixed operation code in original commit message (0xEH -> 0xEB)

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 16:01:29 +05:30
Adam Ford
90d76f812b spi: nxp_fspi: Fix error reporting
On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the
rate the clock was able to set.  When checking for errors, it only
checks that it is not NULL.  Since positive numbers are not errors,
only check for negative numbers when handling errors.

Fixes: 383fded70c ("spi: nxp_fspi: new driver for the FlexSPI controller")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 15:09:38 +05:30
Marek Behún
2f0c18b158 ddr: marvell: a38x: fix comment in conditional macro
The code was processed with unifdef utility to omit portions not
relevant to A38x and DDR3. This removes usage of many macros, including
A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove
the macros from #else comment.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
b1b17f8967 ddr: marvell: a38x: bump version to 14.0.0
Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the
version in the mv-ddr-devel branch of upstream repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.

There is a new version numbering system, where after 18.12.0 came
1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
heaterC
420e106ef1 ddr: marvell: a38x: enum mv_ddr_twin_die: change order
commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream.

@pali suggested this change
In commit 6285efb ("mv_ddr: add support for twin-die combined memory
device") was added support for twin-die combined memory device and
default value for explicitly uninitialized structure members is zero, s
also twin_die_combined is initialized to zero. Which means COMBINED
value.
As prior this commit there was no support for twin-die combined memory
device, default value for twin_die_combined should be NOT_COMBINED. This
change change order of enum mv_ddr_twin_die to ensure that NOT_COMBINED
has value zero.

Signed-off-by: heaterC <airyguy@gmx.de>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
a267943fd9 ddr: marvell: a38x: import code change from upstream
commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes code in ddr3_training.c.

Import this change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
2ab7bbf71e ddr: marvell: a38x: fix memory cs size function
commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream.

The funtion returnd cs size in byte instead of MB, that cause
calculation error since the caller was expected to get u32 and when he
got above 4G it refers it as 0.
The fix was to get the cs memory size from function as in MB and then
multiply it by 1MB.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
b85c6fb065 ddr: marvell: a38x: import header change from upstream
commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
44aeb28c9b ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bit
commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream.

WL phase correcion stage is failing while using bus_width of 16bit, not
to be fix this stage is un-necessary when working with bus_width of 16
bit.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
32e7a6baef ddr: marvell: a38x: add support for twin-die combined memory device
commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream.

the twin-die combined memory device should be treatened as X8
device and not as X16 one

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
[ - the default value for twin_die_combined is set to NOT_COMBINED for
    all boards, as this was default behaviour prior this change ]
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
52dd9b96fc ddr: marvell: a38x: add 16Gbit memory devices support
commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Baruch Siach
369e532691 ddr: marvell: a38x: allow board specific ODT configuration
commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream.

The ODT enable heuristic based on active chip-selects is not always
correct. Some board might use two chip-selects, but have only one ODT
line connected. Allow board specific mv_ddr_topology_map to directly set
the ODT configuration register value.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
6e0532401b ddr: marvell: a38x: import header change from upstream
commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
9c4e06af0b ddr: marvell: a38x: fix memory size calculation using 32bit bus width
commit ab9240402a70cc02496683971779e75eff410ab4 upstream.

- function mv_ddr_spd_die_capacity_user_get() has a bug,
  since it insert a user memory enum to it,
  instead of SPD memory enum (which are different)
- fix: remove mv_ddr_spd_die_capacity_user_get() function.
- memory size with 64 and 32 bit already calculated correctly
  at mv_ddr_mem_sz_per_cs_get() function

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Stefan Chulski <Stefan.Chulski@cavium.com>
Reviewed-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
6373a92d42 ddr: marvell: a38x: fix 32bit
commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
4d676739b9 ddr: marvell: a38x: import header change from upstream
commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header mv_ddr_topology.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00