3 Commits

Author	SHA1	Message	Date
Lukas Auer	b2c860c6dc	riscv: fix use of incorrectly sized variables ... The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in several places. Fix this. In addition, BITS_PER_LONG is set to 64 on RV64I systems. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>	2018-11-26 13:57:29 +08:00
Rick Chen	bc0818a6a9	riscv: checkpatch: Fix Macro argument reuse ... It is CHECK reported by checkpatch.pl CHECK: Macro argument reuse 'PTE' - possible side-effects? Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>	2018-03-30 13:13:22 +08:00
Rick Chen	6020faf62c	riscv: nx25: include: Add header files to support RISC-V ... Add header files for RISC-V. Cache, ptregs, data type and other definitions are included. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>	2018-01-12 08:05:12 -05:00