3 Commits

Author	SHA1	Message	Date
York Sun	316f0d0f8f	powerpc: mpc85xx: Fix static TLB table for SDRAM ... Most predefined TLB tables don't have memory coherence bit set for SDRAM. This wasn't an issue before invalidate_dcache_range() function was enabled. Without the coherence bit, dcache invalidation doesn't automatically flush the cache. The coherence bit is already set when dynamic TLB table is used. For some boards with different SPL boot method, or with legacy fixed setting, this bit needs to be set in TLB files. Signed-off-by: York Sun <york.sun@nxp.com>	2017-12-06 14:54:12 -08:00
Tom Rini	5b8031ccb4	Add more SPDX-License-Identifier tags ... In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>	2016-01-19 08:31:21 -05:00
Dirk Eibach	b9944a77f9	mpc85xx: Add gdsys ControlCenter Digital board ... The gdsys ControlCenter Digital board is based on a Freescale P1022 QorIQ SOC. It boots from SPI-Flash but can be configured to boot from SD-card for factory programming and testing. On board peripherals include: - 2x GbE - Lattice ECP3 FPGA connected via PCIe - mSATA RAID1 - USB host - DisplayPort video output - Atmel TPM Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc> Signed-off-by: Andy Fleming <afleming@freescale.com>	2013-07-16 17:44:30 -05:00