Commit Graph

5 Commits

Author SHA1 Message Date
Stephen Warren
fcf2ede190 usb: ci_udc: support variants with hostpc register
Tegra's USB controller appears to be a variant of the ChipIdea
controller; perhaps derived from it, or simply a different version of
the IP core to what U-Boot supports today.

In this variant, at least the following difference are present:
- Some registers are moved about.
- Setup transaction completion is reported in a separate 'epsetupstat'
  register, rather than in 'epstat' (which still exists, perhaps for
  other transaction types).
- USB connection speed is reported in a separate 'hostpc1_devlc'
  register, rather than 'portsc'.
- The registers used by ci_udc.c begin at offset 0x130 from the USB
  register base, rather than offset 0x140. However, this is handled
  by the associated EHCI controller driver, since the register address
  is stored in controller.ctrl->hcor.

Introduce define CONFIG_CI_UDC_HAS_HOSTPC to indicate which variant of
the controller should be supported. The "HAS_HOSTPC" part of this name
mirrors the similar "has_hostpc" field used by the Linux EHCI controller
core to represent the presence/absence of the hostpc1_devlc register.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-04-30 10:30:57 +02:00
Stephen Warren
0c51dc6db9 usb: ci_udc: make PHY initialization conditional
usb_gadget_register_driver() currently unconditionally programs PORTSC
to select a ULPI PHY. This is incorrect on at least the Tegra boards I
am testing with, which use a UTMI PHY for the OTG ports. Make the PHY
selection code conditional upon the specific EHCI controller that is in
use.

Ideally, I believe that the PHY initialization code should be part of
ehci_hcd_init() in the relevant EHCI controller driver, or some board-
specific function that ehci_hcd_init() calls.

For MX6, I'm not sure this PHY initialization code is correct even before
this patch, since ehci-mx6's ehci_hcd_init() already configures PORTSC to
a board-specific value, and it seems likely that the code in ci_udc.c is
incorrectly undoing this. Perhaps this is not an issue if the PHY
selection register bits aren't implemented on this instance of the MX6
USB controller?

ehci-mxs.c doens't appear to touch PORTSC, so this code is likely still
required there.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-04-30 10:30:57 +02:00
Stephen Warren
8aac6e9c53 usb: ci_udc: set ep->req.actual after transfer
At least drivers/usb/gadget/storage_common.c expects that ep->req.actual
contain the number of bytes actually transferred. (At least in practice,
I observed it failing to work correctly unless this was the case).

However, ci_udc.c modifies ep->req.length instead. I assume that .length
 is supposed to represent the allocated buffer size, whereas .actual is
supposed to represent the actual number of bytes transferred. In the OUT
transaction case, this may happen simply because the host sends a smaller
 packet than the max possible size, which is quite legal. In the IN case,
transferring fewer bytes than requested could presumably happen as an
error.

Modify handle_ep_complete() to write to .actual rather than modifying
.length.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-04-30 10:30:57 +02:00
Stephen Warren
f5c03006dd usb: ci_udc: Support larger packets
ci_ep_queue() currently only fills in the page0/page1 fields in the
queue item. If the buffer is larger than 4KiB (unaligned) or 8KiB
(page-aligned), then this prevents the HW from knowing where to write
the balance of the data.

Fix this by initializing all 5 pageN pointers, which allows up to
16KiB (potentially non-page-aligned) buffers.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-04-30 10:30:57 +02:00
Marek Vasut
f016f8ca3d usb: mv_udc: Rename to ci_udc
The mv_udc is not marvell-specific anymore. The mv_udc is used to drive
generic ChipIdea CI13xxx series OTG cores, so rename the driver to ci_udc
instead.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Stefano Babic <sbabic@denx.de>
2014-02-06 04:48:15 +01:00