Now that coreboot doesn't need the start16 code, remove it. We need
to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Putting global data on the stack simplifies the init process (and makes it
slightly quicker). During the 'flash' stage of the init sequence, global
data is in the CAR stack. After SDRAM is initialised, global data is copied
from CAR to the SDRAM stack
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
board configuration file is included before asm/config_mpc85xx.h.
however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h.
it will never take effective in the board configuration file for
this kind of code :
#ifdef CONFIG_FSL_SATA_V2
...
#endif
To solve this problem, move CONFIG_FSL_SATA_V2 to board
configuration header file.
This patch reverts Timur's
commit:3e0529f742e893653848494ffb9f7cd0d91304bf
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet
connector. It is necessary to use the same base address for correct LAW
address. An offset is added for NOR flash.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning
of this virtual bank so that this bank can store RCW or be used together
with other banks to store large images.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In
some cases (e.g. user load commands) this cannot be guaranteed by callers
of the MMC APIs. To solve this, modify the Tegra MMC driver to use the
new bounce_buffer_*() APIs.
Note: Ideally, all U-Boot code will always provide address- and size-
aligned buffers, so a bounce buffer will only ever be needed for user-
supplied buffers (e.g. load commands). Ensuring this removes the need
for performance-sucking bounce buffer cache management and memcpy()s.
The one known exception at present is the SCR buffer in sd_change_freq(),
which is only 8 bytes long. Solving this requires enhancing struct
mmc_data to know the difference between buffer size and transferred data
size, or forcing all callers of mmc_send_cmd() to have allocated buffers
using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not
enforced in any way at present, and so cannot be assumed by the core MMC
code.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Commits 6dc71c8 "MMC: MXS: Toggle the generic bounce buffer on the
boards" and 49a627f "MMC: Remove the MMC bounce buffer" replaced
CONFIG_MMC_BOUNCE_BUFFER with CONFIG_BOUNCE_BUFFER, but missed
converting a few boards over to the new option. Fix this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data. The SPL itself cannot use SPD due
to code size constraints. It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with. It's possible that different revisions of the board
require different settings. Using SPD eliminates that problem.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
- Sort by address, and fix column alignment
- Don't label things as localbus that aren't. Instead, put chipselect
info at the end of the description for localbus windows. Note that
NAND/NOR have their chipselects swapped when booting from NAND, and CS2
can be either PMC or VSC7385 depending on hwconfig.
- Shrink NAND to the 32K that's actually mapped in the localbus
- Assign an address and size to L2 SRAM. Remove the similarly named
but unintelligible "L2 SDRAM(REV.)".
- Remove the untrue comment about L1 stack being mapped with TLB0.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Some small SPLs do not use nand_base.c, and a subset of those also
require a special driver. Some SPLs need software ECC but others can't
fit it.
All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these
symbols added to preserve existing behavior.
Signed-off-by: Scott Wood <scottwood@freescale.com>
--
v2: use positive logic for including bits of NAND, rather than
a MINIMAL symbol that excludes things.
Enable using of new MUSB framework on Beagle.
NOTE! This is not just a change of backend code: top-level behavior
is also changed, we now use USB device port for USB Ethernet instead
of serial.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Enable USB keyboard for seaboard and ventana
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Move environment settings for stdin/stdout/stderr to
tegra-common-post.h and generate them automaticaly based on input
device selection.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
CONFIG_EHCI_DCACHE was removed by commit b8adb12
"USB: Drop cache flush bloat in EHCI-HCD". Remove the defines from
the boards configs as well.
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
cc: Marek Vasut <marex@denx.de>
cc: Stefan Roese <sr@denx.de>
cc: Tom Rini <trini@ti.com>
cc: Wolfgang Denk <wd@denx.de>
cc: Thierry Reding <thierry.reding@avionic-design.de>
cc: Tom Warren <twarren@nvidia.com>
cc: Stephen Warren <swarren@nvidia.com>
cc: Stefano Babic <sbabic@denx.de>
- update clock settings for higher perfomance
- change standard baud rate to 115200
- fix flash base address
- remove unused defines
- add I2C support
- switch form board dependent flash to cfi
- remove board dependent flash code
- use sdram bank 0 instead of bank 1 on boot
- enable on board frame buffer instead external
- remove fake mac address form config
- add watchdog support
- add status led support
Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
[agust: fixed small style issues and build warning]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Support for TRATS battery has been added. It is treated as a "normal"
power related device and thereof controlled by pmic/power subsystem.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
FG IC built into the MAX8997 device (compliant to MAX17042) is enabled
at TRATS.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
MUIC IC built into the MAX8997 device is enabled at TRATS.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
The file has a wrong inline keyword of __led_toggle(), which causes
compilation error. And its content is defined in common status_led.h.
So define CONFIG_BOARD_SPECIFIC_LED in board config files and remove
this header file.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Flushing caches is necessary because of soft reset
which doesn't clear caches.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Reviewed-by: Marek Vasut <marex@denx.de>
We add CONFIG_ENV_VARS_UBOOT_CONFIG,
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and CONFIG_BOARD_LATE_INIT to set
the variables and then fdtfile and findfdt to make us of this. It is
now possible to do 'run findfdt' to have fdtfile be set to the value of
the dtb file to load for the board we are running on.
Signed-off-by: Tom Rini <trini@ti.com>
Commit 1db7377a70 fixes the gen_atmel_mci driver
to be able to use multi block access for avr32. Therefore remove the setting
which forces single block access.
This also adds a huge performace gain for mmc access:
---8<---
Loading file "/boot/uImage" from mmc device 0:1
1830666 bytes read in 1293 ms (1.3 MiB/s)
--->8---
vs.
---8<---
Loading file "/boot/uImage" from mmc device 0:1
1830666 bytes read in 237 ms (7.4 MiB/s)
--->8---
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: haavard.skinnemoen@atmel.com
Cc: hans-christian.egtvedt@atmel.com
Cc: mpfj@mimc.co.uk
Cc: alex.raimondi@miromico.ch
Cc: julien.may@miromico.ch
Cc: egtvedt@samfundet.no
Cc: havard@skinnemoen.net
Change tegra SPL to use common SPL framework. Any tegra specific
initialization is now done in spl_board_init() instead of
board_init_f()/board_init_r(). Only one SPL boot target is supported
on tegra, which is boot to RAM image. jump_to_image_no_args() must be
overridden on tegra so the host CPU can be initialized.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
For Tegra, the SPL and main U-Boot are concatenated together to form a
single memory image. Hence, the maximum SPL size is the different in
TEXT_BASE for SPL and main U-Boot. Instead of manually calculating
SPL_MAX_SIZE based on those two TEXT_BASE, which can lead to errors if
one TEXT_BASE is changed without updating SPL_MAX_SIZE, simply perform
the calculation automatically.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Allen Martin <amartin@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add the missing bits to the Tegra NAND driver to make ONFI detection work
properly.
Also add it to the Tegra default config, as it seems to be a reasonable thing
to have it available on all boards that use any kind of NAND.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The device tree already contains the required configuration for both the
USB1 and USB3 ports. Enable the required configuration options to enable
both these ports, which in turn allows the USB1 port to be used.
Note that on a true Seaboard, this port is typically used as a device
port hosting Tegra's USB recovery protocol. However, on the Springbank
derivative, this port is the only external USB port, so we enable it as
a host port so that USB peripherals may be used. Enabling this port in
U-Boot as a host port doesn't prevent the port from reverting to a
device port when the CPU is reset into recovery mode.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The ULPI port is routed onto pins on the mini PCI Express connector. A
standard breakout board may be used to access the port.
* Add required DT entries to configure the ULPI port.
* Setup up the ULPI pinmux in the board code.
* Enable multiple USB controller and ULPI support in the board config.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
