Commit Graph

31 Commits

Author SHA1 Message Date
Michal Simek
0ebf40417d net: zynq: Fix clearing statistic
Previous loop was completely bogus. Iterration should go just over
statistic counters.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-11-19 13:09:21 +01:00
Michal Simek
97a51a0363 net: zynq: Extend register description with offsets
Extend comments with register offset to help with debuggging.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-11-19 13:09:21 +01:00
Michal Simek
16ce6de87e net: zynq: Add support for different PHY interface types
MII is setup by default for all cases. The most of boards are using
RGMII but PHY drivers are not doing any specific setting that's why MII
setting was working fine. With TI DP83867 is necessary to setup
paramaters based on interface type.

Use one setting per board for it which is something what will be removed
when driver is moved to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-11-19 13:09:21 +01:00
Michal Simek
198e9a4fe9 net: zynq: Add debug message to phyread/phywrite
Add debug messages to phyread/write to help with PHY debug.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-11-19 13:09:21 +01:00
Prabhakar Kushwaha
5b47d407e4 driver: net: Fix pointer conversion warnings for xilinx_zynqmp_ep
Fix below warnings happening for xilinx_zynqmp_ep_defconfig

drivers/net/zynq_gem.c: In function ‘zynq_gem_init’:
drivers/net/zynq_gem.c:330:7: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
      ((u32)(priv->rxbuffers) +
       ^
In file included from drivers/net/zynq_gem.c:19:0:
drivers/net/zynq_gem.c:336:10: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
   writel((u32)priv->rx_bd, &regs->rxqbase);
          ^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro ‘writel’
 #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
                                  ^
drivers/net/zynq_gem.c: In function ‘zynq_gem_send’:
drivers/net/zynq_gem.c:399:9: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
  writel((u32)priv->tx_bd, &regs->txqbase);
         ^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro ‘writel’
 #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
                                  ^
drivers/net/zynq_gem.c:404:22: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
  priv->tx_bd->addr = (u32)ptr;
                      ^
drivers/net/zynq_gem.c:409:9: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
  addr = (u32) ptr;
         ^
drivers/net/zynq_gem.c:414:9: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
  addr = (u32)priv->rxbuffers;
         ^
drivers/net/zynq_gem.c: In function ‘zynq_gem_recv’:
drivers/net/zynq_gem.c:454:31: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
   net_process_received_packet((u8 *)addr, frame_len);
                               ^
drivers/net/zynq_gem.c: In function ‘zynq_gem_initialize’:
drivers/net/zynq_gem.c:533:35: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
  priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);
                                   ^
drivers/net/zynq_gem.c:533:16: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
  priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2015-11-12 15:59:00 -05:00
Masahiro Yamada
0f9258228e of: clean up OF_CONTROL ifdef conditionals
We have flipped CONFIG_SPL_DISABLE_OF_CONTROL.  We have cleansing
devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear
away the ugly logic in include/fdtdec.h:

 #ifdef CONFIG_OF_CONTROL
 # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL)
 #  define OF_CONTROL 0
 # else
 #  define OF_CONTROL 1
 # endif
 #else
 # define OF_CONTROL 0
 #endif

Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute.  It refers to
CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for
SPL.

Also, we no longer have to cancel CONFIG_OF_CONTROL in
include/config_uncmd_spl.h and scripts/Makefile.spl.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-08-18 13:46:05 -04:00
Michal Simek
4c8b7bf49f net: gem: Extend timeout value
Extend time for MDIO. (Because of zed board)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:28 +02:00
Michal Simek
e65d33cf03 zynq: gem: Setting up WRAP bit for one TX bd
Setting up WRAP bit to indicate that this is the last TX BD in the
chain.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:18 +02:00
Siva Durga Prasad Paladugu
eda9d3071b zynq: gem: Increase the Rx buffer descriptors to 32
Increase the Rx Buffer descriptors to 32. This will avoid
Rx buffer descriptors overflow if more packets were received
at one shot before we process the received ones.
This fixes the issue of intermittent timeouts during tftp
on a 1Gb connection with tftp server running on windows.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:18 +02:00
Siva Durga Prasad Paladugu
96f4f14964 zynqmp: gem: Flush the rx buffers while transmitting
Flush and invalidate the rx buffers while sending the
tx packet it self as armv8 does flush also while doing
invalidation.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:18 +02:00
Siva Durga Prasad Paladugu
8a584c8a7f zynqmp: gem: Set data bus width to 64bit for arm64
Set the data bus width to 64-bit AMBA Databus width in config register.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-07-28 11:56:18 +02:00
Michal Simek
9ce1edc8d0 net: gem: Use correct type for casting
Use phys_addr_t which is used in function prototype
in system.h.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-04-20 17:57:13 -05:00
Joe Hershberger
1fd92db83d net: cosmetic: Fix var naming net <-> eth drivers
Update the naming convention used in the network stack functions and
variables that Ethernet drivers use to interact with it.

This cleans up the temporary hacks that were added to this interface
along with the DM support.

This patch has a few remaining checkpatch.pl failures that would be out
of the scope of this patch to fix (drivers that are in gross violation
of checkpatch.pl).

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:33 -06:00
Michal Simek
5840537879 net: gem: Use phys_addr_t instead of int for addresses
Use phys_addr_t for physical address declaration.
It is also unsigned type instead of sign.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-21 10:30:21 +01:00
Michal Simek
2fd2489b7a net: zynq: Fix sparse warnings in gem
Add missing header.

Warnings:
drivers/net/zynq_gem.c:491:5: warning: symbol 'zynq_gem_initialize' was not declared. Should it be static?
drivers/net/zynq_gem.c:542:5: warning: symbol 'zynq_gem_of_init' was not declared. Should it be static?

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-06 13:41:55 +02:00
Michal Simek
c1a9fa4ba6 net: zynq: Use predefined macros instead of hardcoded value
MII is used by this driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-06 13:41:33 +02:00
Michal Simek
f88a6869a1 net: gem: Add OF initialization support
Gem can be directly initialized from DTB.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-03-04 09:27:35 -05:00
Soren Brinkmann
97598fcf10 net: zynq_gem: Calculate clock dividers dynamically
Remove hard coded clock divider setting and use the Zynq clock framework
to dynamically calculate appropriate dividers at run time.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19 09:41:21 +01:00
Soren Brinkmann
1cd46ed2d3 net: zynq_gem: Move RCLK details out of driver
The GEM driver should not need to know about Zynq specific details of
RCLK related registers and bitfields in the SLCR. Move those details to
the slcr driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-19 09:41:21 +01:00
Michal Simek
4ed4aa20de net: gem: Check if phy was correctly detected
As tsec and fm drivers checking phydev->link
ensure that u-boot don't try access device if link is not ready.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-01-21 16:07:10 +01:00
Srikanth Thokala
a5144237ac net: zynq_gem: Add d-cache support
Added d-cache support for zynq_gem.c,
Observed a difference of +0.8 MiB/s when downloading
a file of size of 3007944Bytes.

With d-cache OFF:
----------------
Filename 'uImage'.
Load address: 0x800
Loading: #################################################################
         #################################################################
         #################################################################
         ##########
         1.3 MiB/s
done
Bytes transferred = 3007944 (2de5c8 hex)

With d-cache ON:
---------------
Filename 'uImage'.
Load address: 0x800
Loading: #################################################################
         #################################################################
         #################################################################
         ##########
         2.1 MiB/s
done
Bytes transferred = 3007944 (2de5c8 hex)

Changes on zynq_gem for d-cache support:
- Tx and Rx buffers are cache-aligned
- Updated logic for invalidating Rx buffers and flushing Tx buffers.
- Tx and Rx BD's are allocated from non-cacheable region.
  (When BDs are cached, we don't see a consistent link)
- Use TX BD status intead of txsr status checks.

Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-11-22 17:03:20 -06:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Michal Simek
f97d7e8be9 net: gem: Add support for phy autodetection
Autodetect phy if phyaddress is setup to -1.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:26 +02:00
David Andrey
01fbf31042 net: gem: Preserve clk on emio interface
Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL
if the Ethernet interface is connect on EMIO

Do not enable emio for this standard board configuration for now.

Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:24 +02:00
David Andrey
117cd4cc10 net: gem: Pass phy address to init
Pass the PHY address to the driver init to
allow parallel use of both interfaces

Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:23 +02:00
Michal Simek
80243528ef net: gem: Fix gem driver on 1Gbps LAN
The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:19 +02:00
Michal Simek
058687597d net: gem: Do not initialize BDs again
BDs can be correctly setup just once and init function
performs only phy autodetection and enabling RX/TX.
RX/TX are disabled in halt function.

This patch solves the problem with repeatable tftp transfers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:17 +02:00
Michal Simek
3b90d0afe5 net: gem: Simplify return path in zynq_gem_recv
Remove one return from the code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:16 +02:00
Michal Simek
986f00003c net: gem: Remove WRAP bit from TX buffer description
Removing this bit causes that frame is sent only once.
(With wrap big one packet has been sent several times
which dramatically decrease throughput)

TRM: (Table 16-3: Tx Buffer Descriptor Entry)

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:14 +02:00
Michal Simek
185f7d9afc net: Add driver for Zynq Gem IP
Device driver for Zynq Gem IP.

Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Joe Hershberger <joe.hershberger@gmail.com>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2012-09-26 12:36:32 -05:00