CAS-Latency=2, Write Recovery Time tWR=2
The max. supported bus frequency is 66 MHz. Therefore, changed
threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
As reported by Gerhard Berghofer:
in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18
instead of PB18 and PB19.
which is obviously correct. There's currently no code that uses
USART3, but custom boards may run into problems.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Add a chip-features file providing definitions of the form
AT32AP700x_CHIP_HAS_<peripheral>
to indicate the availability of the given peripheral on the currently
selected chip.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
The SoC-specific code for all the AT32AP700x CPUs is practically
identical; the only difference is that some chips have less features
than others. By doing this rename, we can add support for the AP7000
derivatives simply by making some features conditional.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
The MPC8572 introduces the concept of an asynchronous DDR clock with
regards to the platform clock.
Introduce get_ddr_freq() to report the DDR freq regardless of sync/async
mode.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_*_ADDR as the base of the registers
instead of getting it via &immap.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers
instead of getting it via &immap->im_cpm.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers
instead of getting it via &immap->im_gur.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Update libfdt to commit 8eaf5e358366017aa2e846c5038d1aa19958314e from
the device tree compiler (dtc) project.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Moved the generic fixup handling code out of cpu/mpc5xxx and cpu/mpc8260
into common/fdt_support.c and renamed:
do_fixup() -> do_fixup_by_path()
do_fixup_u32() -> do_fixup_by_path_u32()
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
au1x00_eth.c: In function 'au1x00_miiphy_write':
au1x00_eth.c:139: warning: 'return' with no value, in function returning non-void
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
au1x00_eth.c: In function 'au1x00_enet_initialize':
au1x00_eth.c:246: error: 'au1x00_miiphy_read' undeclared (first use in this function)
au1x00_eth.c:246: error: (Each undeclared identifier is reported only once
au1x00_eth.c:246: error: for each function it appears in.)
au1x00_eth.c:246: error: 'au1x00_miiphy_write' undeclared (first use in this function)
au1x00_eth.c: In function 'au1x00_miiphy_write':
au1x00_eth.c:298: warning: 'return' with no value, in function returning non-void
make[1]: *** [au1x00_eth.o] Error 1
Fixed by moving these two functions forward.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Ugh. I *hate* to back this change out, but these compiler flags don't
work for relocation on all versions of GCC. I've not been able to
reproduce the environment in my setup (and hence, not been able to
find a combination that *does* work), so I've got no choice but to go
back to the old gcc flags and linker script.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Since December 2003 the timer_interrupt_cpu() function in
cpu/mpc824x/interrupts.c contains what seems to be a superfluous
parameter. Remove it.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
The pxa255_idp being an old unmaintained board showed several issues:
1. CONFIG_INIT_CRITICAL was still defined.
2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined.
3. Symbol flash_addr was undeclared.
4. The boards lowlevel_init function was still called memsetup.
5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000.
6. Using -march=armv5 instead of -march=armv5te resulted in lots of
'target CPU does not support interworking' warnings on recent compilers.
7. The PXA's serial driver redefined FFUART, BTUART and STUART used as
indexes rather than the register definitions from the pxa-regs header
file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to
avoid any ambiguities.
8. There were several redefinition warnings concerning ICMR, OSMR3,
OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file.
9. The board configuration file was rather outdated.
10. The part header file defined the vendor, product and revision arrays
as unsigned chars instead of just chars in the block_dev_desc_t
structure.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
