Commit Graph

10 Commits

Author SHA1 Message Date
Rick Chen
0d389468e2 riscv: Add a SYSCON driver for Andestech's PLIC
The Platform-Level Interrupt Controller (PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt. It is required
for handling IPI.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
Lukas Auer
f152febb2a riscv: implement IPI platform functions using SBI
The supervisor binary interface (SBI) provides the necessary functions
to implement the platform IPI functions riscv_send_ipi() and
riscv_clear_ipi(). Use it to implement them.

This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
running in supervisor mode. Support for machine mode is already
available for CPUs that include the SiFive CLINT.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:26 +08:00
Lukas Auer
fa33f08fd6 riscv: add infrastructure for calling functions on other harts
Harts on RISC-V boot independently, U-Boot is responsible for managing
them. Functions are called on other harts with smp_call_function(),
which sends inter-processor interrupts (IPIs) to all other available
harts. Available harts are those marked as available in the device tree
and present in the available_harts mask stored in global data. The
available_harts mask is used to register all harts that have entered
U-Boot. Functions are specified with their address and two function
arguments (argument 2 and 3). The first function argument is always the
hart ID of the hart calling the function. On the other harts, the IPI
interrupt handler handle_ipi() must be called on software interrupts to
handle the request and call the specified function.

Functions are stored in the ipi_data data structure. Every hart has its
own data structure in global data. While this is not required at the
moment (all harts are expected to boot Linux), this does allow future
expansion, where other harts may be used for monitoring or other tasks.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:25 +08:00
Anup Patel
511107d85d riscv: Implement riscv_get_time() API using rdtime instruction
This adds an implementation of riscv_get_time() API that is using
rdtime instruction.

This is the case for S-mode U-Boot, and is useful for processors
that support rdtime in M-mode too.

Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-18 09:56:27 +08:00
Bin Meng
644a3cd77e riscv: Add a SYSCON driver for SiFive's Core Local Interruptor
This adds U-Boot syscon driver for SiFive's Core Local Interruptor
(CLINT). The CLINT block holds memory-mapped control and status
registers associated with software and timer interrupts.

This driver implements the riscv_get_time() API as required by
the generic RISC-V timer driver, as well as some other APIs that
are needed for handling IPI.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:26 +08:00
Bin Meng
b984ddc2dd riscv: Move do_reset() to a common place
We don't have a reset method on any RISC-V board yet. Instead of
adding the same 'unsupported' message for each CPU variant it might
make more sense to add a generic do_reset function for all CPU
variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c).

Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:43 +08:00
Alexander Graf
493d1e88b6 riscv: Add EFI application infrastructure
The hello world binary and a few selftests require to build EFI target
binaries, not just the EFI host environment.

This patch adds all required files to generate an EFI binary for
RISC-V.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Alexander Graf
a7f99e5dd7 riscv: Add setjmp/longjmp code
To support efi_loader we need to have platform support for setjmp/longjmp.
Add it here.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Rick Chen
8bbb2909cb riscv: nx25: lib: Add relative lib funcs to support RISC-V
Add makefile, interrupts.c and boot.c,... functions
to support RISC-V arch.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12 08:05:12 -05:00