Commit Graph

51807 Commits

Author SHA1 Message Date
Simon Glass
3ab9598df7 binman: Rename 'position' to 'offset'
After some thought, I believe there is an unfortunate naming flaw in
binman. Entries have a position and size, but now that we support
hierarchical sections it is unclear whether a position should be an
absolute position within the image, or a relative position within its
parent section.

At present 'position' actually means the relative position. This indicates
a need for an 'image position' for code that wants to find the location of
an entry without having to do calculations back through parents to
discover this image position.

A better name for the current 'position' or 'pos' is 'offset'. It is not
always an absolute position, but it is always an offset from its parent
offset.

It is unfortunate to rename this concept now, 18 months after binman was
introduced. However I believe it is the right thing to do. The impact is
mostly limited to binman itself and a few changes to in-tree users to
binman:

   tegra
   sunxi
   x86

The change makes old binman definitions (e.g. downstream or out-of-tree)
incompatible if they use the 'pos = <...>' property. Later work will
adjust binman to generate an error when it is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-08-01 16:30:06 -06:00
Simon Glass
46d61a2f2a binman: Don't depend on dict order in ELF testOutsideFile()
At present this test assumes that the symbols are returned in address
order. However, objdump can list symbols in any order and dictionaries do
not guarantee any particular order when iterating through item.

Update elf.GetSymbols() to return an OrderedDict, sorted by address, to
avoid any problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-08-01 16:27:28 -06:00
Yannick Fertré
28576f8182 dm: panel: get timings from panel
Get timings from panel instead of read device tree.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-01 18:03:58 +02:00
Tom Rini
61523dde17 Merge tag 'arc-updates-for-2018.09-rc2' of git://git.denx.de/u-boot-arc
That's a set of prety minor changes and fixes for ARC.

Among them:
 * Improvement in CREG GPIO driver used on ARC dev boards
   that allow us to re-use the driver for SPI's chip select

 * Enable SPI-flsh on AXS10x boards which allows to update
   U-Boot binary that gets loaded by boot-ROM

 * Fix accommodating always utilized unaligned access by
   GCC for ARC starting from 8.1.0
2018-08-01 09:26:15 -04:00
Luis Araneda
ba71ab8246 video: kconfig: remove DM_I2C dependency of I2C_EDID
Drop the DM_I2C dependency, as the library only implements
the parsing of EDID data and doesn't depend on any driver

One user of this library, the i2c command, implements
support for legacy and DM I2C drivers

Tested on a Zynq board, whose I2C driver is not ported
yet to DM

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
2018-08-01 14:45:14 +02:00
Tom Rini
20a619c617 Merge git://git.denx.de/u-boot-mpc85xx 2018-07-31 20:01:30 -04:00
Tom Rini
ae5afc3720 .travis.yml: Exclude openrd platforms
The openrd platforms are currently orphaned, and are constantly on-edge
or overflowing their binary limit.  Exclude them from travis for now.

Cc: Vagrant Cascadian <vagrant@debian.org>
Cc: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-31 19:58:23 -04:00
Tom Rini
d150d6131c .travis.yml: Exclude kirkwood machines from the arm926ejs job
We have a specific job for kirkwood platforms so exclude them from this
job.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-31 19:58:23 -04:00
Tom Rini
e93db9b6ca openrd: Mark as Orphaned
After talking with Albert, mark these boards as orphaned as he no longer
has one.

Cc: Albert ARIBAUD <albert-u-boot@aribaud.net>
Cc: Vagrant Cascadian <vagrant@debian.org>
Cc: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-31 19:58:22 -04:00
Tom Rini
781e8f6cb1 ls1046ardb: Add qspi_spl variant to the MAINTAINERS file
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-31 14:53:18 -04:00
Tom Rini
275906dc1b pico-pi: Add Otavio as maintainer
Update the MAINTAINERS file to list Otavio Salvador as the maintainer
for this board.

Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-31 14:47:01 -04:00
Michal Simek
b3815fc4e5 dm: Fix CMD_DM enabling
The patch "dm: Change CMD_DM enabling"
(sha1: 08a00cba06) was incorrectly updated
and PICO_IMX7D is missing imply CMD_DM and WARP7 has it twice.
This patch is fixing it.

Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-31 14:46:22 -04:00
Ran Wang
9dcb9d763d Revert "powerpc/T104xRDB: Fix endian access issue on EHCI intinalization"
There was an EHCI endian accessor issue. Now it's fixed by commit
9829ce2ff2 ("usb: ehci: Fix accessors for big-endian platforms and
descriptors"). Revert commit e6a727fffe ("powerpc/T104xRDB: Fix
endian access issue on EHCI intinalization"). On T104x platform,
USB EHCI register use little endian.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-07-31 10:19:42 -07:00
Ran Wang
9a21dc3726 Revert "powerpc/p1_p2_rdb_pc: Fix endian access issue on EHCI intinalization"
There was an EHCI endian accessor issue. Now it's fixed by commit
9829ce2ff2 ("usb: ehci: Fix accessors for big-endian platforms and
descriptors"). Revert commit 0f2296bab1 ("powerpc/p1_p2_rdb_pc:
Fix endian access issue on EHCI intinalization"). On P1 P2 platforms,
USB EHCI register use little endian.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-07-31 10:17:18 -07:00
Jagan Teki
89a897fc4d board: sun50i: h6: Add OrangePi One Plus initial support
OrangePi One Plus is Allwinner H6 based open-source SBC,
which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 1GB LPDDR3 RAM
- AXP805 PMIC
- 1Gbps GMAC via RTL8211
- USB 2.0 Host, OTG
- HDMI port
- 5V/2A DC power supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-31 20:50:01 +05:30
Mylène Josserand
850bdafa50 mtd: nand: sunxi: Return on set_feature only when not ENOTSUPP
Return the error code of the set_features function only if
the error code is not ENOTSUPP. Otherwise, if this function
is not supported, it will return and fail to initialize the
NAND.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-07-31 20:45:50 +05:30
Mylène Josserand
cbe9ea26e3 mtd: nand: nand_base: Convert EINVAL into ENOTSUPP
Convert the EINVAL error into ENOTSUPP when the GET/SET_FEATURES
is not supported.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-07-31 20:45:42 +05:30
Jagan Teki
3362094733 configs: sunxi: Drop CONFIG_SUNXI_USB_PHYS
Now number of PHY on Allwinner is handling via dt data,
drivers at phy/allwinner/phy-sun4i-usb.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:43:07 +05:30
Jagan Teki
69aa1b234e phy: sun4i-usb: Update PHY#3 rst_mask only for H3_H5
Only H3 and H5 have 4 PHYS so restrict rst_mask only for them
by checking PHY id as 3 and update the proper bits.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:41:49 +05:30
Jagan Teki
52185b094d phy: sun4i-usb: Remove usb_clk_cfg set in probe
usb_clk_cfg is setting CTRL_PHYGATE bit value in probe
which is BIT 0 for sun4i, 6i and 8 for a83t but all
these were handling in phy ops init exit calls.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:41:45 +05:30
Jagan Teki
0bfcb47aa0 phy: sun4i-usb: Call phy_passby even for PHY#0
On newer Allwinner SoC, there is a pair of EHCI/OHCI USB hosts
for OTG host mode. USB PHY passby must be configured for its
corresponding PHY. so we can call for PHY#0. on the other hand
in past usb-phy code the same thing can be restricted for
Lower SoC's, other than H3/H5/A64.

Now there is no need to restrict usb passby since the phy driver
is DT enabled, and the respective phy calls will trigger based
DT information initiated by the drivers.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:41:41 +05:30
Icenowy Zheng
b29712e941 video: sunxi: de2: fix SimpleFB node creation when DE2 not probed
Sometimes when a monitor without EDID information is plugged, the DE2
won't be probed (because of lack of timing information), but the HDMI
node is probed, thus a SimpleFB node with invalid information will be
populated.

Also detect whether DE2 is probed when creating SimpleFB node.

Fixes: be5b96f0e4 ("sunxi: setup simplefb for Allwinner DE2")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-07-31 11:39:47 +05:30
Icenowy Zheng
a8407b5642 sunxi: add support for Pine H64 board
Pine H64 is a SBC with Allwinner H6 SoC produced by Pine64. It features
1GiB/2GiB/4GiB(3GiB usable) DRAM, two USB 2.0 ports, one USB 3.0 port
and a mPCIE slot.

Add support for it.

The device tree is from Linux next-20180720.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
6f796a9bb4 sunxi: add support for Allwinner H6 SoC
Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe
interfaces.

This patch adds support for it.

The corresponding DTSI file, from Linux next-20180720, is also
introduced.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
da2616543a sunxi: add DRAM support to H6
The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo.
Both the controller and the PHY seem to be originate from DesignWare,
and are similar to the ones in ZynqMP SoCs.

This commit introduces an initial DRAM driver for H6, which contains
only LPDDR3 support. The currently known SBCs with H6 all come with
LPDDR3 memory, including Pine H64 and several Orange Pi's.

The BSP DRAM initialization code is closed source and violates GPL. Code
in this commit is written by experimenting, referring the code/document
of other users of the IPs (mainly the ZynqMP, as it's the only found PHY
reference) and disassebling the BSP blob.

Thanks for Jernej Skrabec for review and fix some issues in this driver
(including the most critical one which made it to work), and rewrite
some code from register dump!

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
42956f1b85 sunxi: add MMC support for H6
The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with
the MMC2 come with the capability to do crypto by EMCE.

Add MMC support for H6. EMCE support is not added yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
7f51a4020e sunxi: add UART0 setup for H6
The UART0 on H6 is available at PH bank (and PF bank, but the PF one is
muxed with SD card).

Add pinmux configuration.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
10196c9627 sunxi: use sun6i-style watchdog for H6
The H6 SoC has a sun6i-style watchdog in its timer part.

Enable the usage of it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
0558676d4b sunxi: add clock code for H6
The new Allwinner H6 SoC has a brand new CCU layout.

Add clock code for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
6958c30319 sunxi: change GIC address on H6
As the Allwinner H6 chip has a new memory map, its GIC MMIO address is
thus different.

Change the address on H6.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
e5715e712a sunxi: add config for SPL at 0x20000 on H6
On the new Allwinner H6 SoC, the SRAM A2 address (SPL load address) is
at 0x20000, which is different with any old Allwinner SoCs.

Add SPL position and size configuration for this.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
0a21fdd62b sunxi: change ATF position for H6
H6 has different SRAM A2 address, so the ATF load address is also
different.

Add judgment code to sunxi 64-bit FIT generation script. It will judge
the SoC by the device tree's name.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
80197801f4 sunxi: change RMR64's RVBAR address for H6
Allwinner H6 has a different RVBAR address with A64/H5.

Add conditional RVBAR configuration into the code which does RMR switch.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
e77b7496c6 sunxi: add basic memory map definitions of H6 SoC
The Allwinner H6 SoC come with a totally new memory map.

Add basical definition of the new memory map into a header file, and let
the cpu.h header include it in the situation of H6.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
cadc7c20e5 sunxi: change SUNXI_HIGH_SRAM option to SUNXI_SRAM_ADDRESS
The new Allwinner H6 SoC has its SRAM A1 at neither 0x0 nor 0x10000, but
it's at 0x20000. Thus the SUNXI_HIGH_SRAM option needs to be refactored
to support this new configuration.

Change it to SUNXI_SRAM_ADDRESS, which holds the real address of SRAM
A1 in the memory map.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Simon Baatz
dddc4b4af3 sunxi: enable SATA on Banana Pi M2 Berry
Banana Pi M2 Ultra and M2 Berry are very similar boards.  SATA can be
enabled exactly the same as for M2 Ultra introduced in
commit daa8b75a55 ("sunxi: enable SATA on Banana Pi M2 Ultra").

Signed-off-by: Simon Baatz <gmbnomis@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-31 11:38:12 +05:30
Alexey Brodkin
8f590063ba ARC: Enable unaligned access in hardware if compiler uses it
Even if ARC core might handle unaligned access to data this
hardware feature by default is disabled.

But GCC starting from 8.1.0 unconditionally uses it for ARC HS cores.
Which leads to quite strange and fatal run-time failures like the one
below if HW is not configured properly:
| hsdk# sf probe
| Misaligned data access exception @ 0xbff794d4
| ECR:    0x000d0000
| RET:    0xbff794d4
| BLINK:  0xbff79644
| STAT32: 0x00000800
| GP: 0x1003e000   r25: 0xbfd58f08
| BTA: 0xbff794a4  SP: 0xbfd58cd4  FP: 0xbfd58ef0
| LPS: 0xbff90240 LPE: 0xbff90244 LPC: 0x00000000
| r00: 0x00000000 r01: 0x00000003 r02: 0x000026bf
| r03: 0x00000000 r04: 0x00000100 r05: 0x00000000
| r06: 0x00000001 r07: 0x00000000 r08: 0x1dcd6500
| r09: 0x00000000 r10: 0x00200000 r11: 0x00000000
| r12: 0x1b3d4440 r13: 0xbff9eca4 r14: 0xbfd59d68
| r15: 0xbfd60cd0 r16: 0x00000000 r17: 0x00000000
| r18: 0xbff9ed14 r19: 0xbfd59c78 r20: 0xbfd58d40
| r21: 0xbfd58d44 r22: 0x00000000 r23: 0x00000000
| r24: 0xbfd59ba8
| Resetting CPU ...

Now we're checking for __ARC_UNALIGNED__ define emitted by the
compiler if it's going to use unaligned access and then we
force-enable it in hardware too.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Alexey Brodkin
164abd1775 HSDK: Fixes and improvements in README
1. Explained prerequisites for "make bsp-generate" command.
2. Cleaned-up duplicates

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Alexey Brodkin
0552e104a5 ARC: AXS10x/HSDK: Use our own version of mkimage
Since U-Boot tools are being built anyways it's much nicer
to use them instead of relying on some of them bein installed
on build host (which might easily not be the case).

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Eugeniy Paltsev
817cd83435 ARC: AXS10x: add tool and make target to generate bsp
AXS10x boards have preloader that reads SPI flash pages and searches
special image header to fetch and load binary.

Add tool, make target (bsp-generate) to generate
update script and u-boot binary image with header for preloader.

Also add script to default environment to apply updates.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Eugeniy Paltsev
cdfe6913c1 AXS10x: add spi flash support
AXS10x boards have n25q512 spi flash IC, so add corresponding
nodes to device tree and enaple corresponding options in
defconfig.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Eugeniy Paltsev
7620ec4df6 CREG GPIO: add device tree bindings
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Eugeniy Paltsev
fe3eb7a887 GPIO: CREG: improve flexibility of hsdk-creg-gpio driver
CREG GPIO is a driver for weird soc-specific output ports, which are
controlled by some fields in memory mapped register.

Example:

31                 9        7        5           0   < bit number
|                  |        |        |           |
[     not used     | gpio-1 | gpio-0 | <-shift-> ]   < 32 bit register
                       ^        ^
                       |        |
                write 0x2 == set output to "1" (activate)
                write 0x3 == set output to "0" (deactivate)

As of tooday we only support fixed (hardcoded) bit per gpio line,
activate / deactivatei and shift values. Fix that by read them from
device tree to be able to use this driver for other boards.

Remove "hsdk" prefix from compatible string as this driver can be
used with different boards like HSDK, AXS101, AXS103, etc.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Tom Rini
5a0007d481 Prepare v2017.09-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-30 21:47:29 -04:00
Tom Rini
f437fea01c fs-test.sh: Update expected result output
Given 0dc1bfb730 ("fs: fat: cannot write to subdirectories") we have
changed how the FAT code works from creating the illegal file "./file"
and instead rejecting the path.  The correct behavior would be to write
"file" to "." but not writing an illegal file is a step in the right
direction.  For now, update the expected output to account for the
failure.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-30 19:56:44 -04:00
Tom Rini
406fd7e207 Patch queue for efi - 2018-07-25
Highlights this time:
 
   - Many small fixes to improve spec compatibility (found by SCT)
   - Almost enough to run with sandbox target
   - GetTime() improvements
   - Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

Patch queue for efi - 2018-07-25

Highlights this time:

  - Many small fixes to improve spec compatibility (found by SCT)
  - Almost enough to run with sandbox target
  - GetTime() improvements
  - Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
2018-07-30 16:02:29 -04:00
Tom Rini
3a8c8bffd7 tpmv2: Make it select CMD_LOG
The TPMv2 code requires the log functionality, so select it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-30 07:18:49 -04:00
Peng Fan
6080170265 tools: genboardscfg: move buildman path to first
To system which has kconfiglib installed, genboardscfg will
use system kconfiglib, we need it use U-Boot owned version,
so move the buildman path to first.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-30 07:18:49 -04:00
Michal Simek
58008cbab5 Kconfig: Sort bool, default, select and imply options
Another round of sorting Kconfig entries aplhabetically.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 07:18:48 -04:00
Michal Simek
08a00cba06 dm: Change CMD_DM enabling
CMD_DM is used for debug purpose and it shouldn't be enabled by default
via Kconfig. Unfortunately this is in the tree for quite a long time
that's why solution is to use imply DM for all targets which are
enabling DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 07:18:48 -04:00