On K3 SoCs, DMA channels are shared across multiple entities, therefore
U-Boot DMA driver needs to query resource range from centralised
resource management controller i.e SystemFirmware and use DMA channels
allocated for A72 host. Add support for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The CORE_TEMP_SENSOR_MPU register gives a raw adc value which needs to
be indexed into a lookup table to get the actual temperature. Fix the
naming and datatype of the adc value variable.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Migrate a few more files]
Signed-off-by: Tom Rini <trini@konsulko.com>
This function has a very generic name which does not adequately describe
its purpose. Rename it and move it to image.h, since it relates to reading
a script from an image.
Signed-off-by: Simon Glass <sjg@chromium.org>
These global variables are quite short and generic. In fact the same name
is more often used locally for struct members and function arguments.
Add a image_ prefix to make them easier to distinguish.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function related to timer and most of the timer functions are in
time.h, so move this function there.
Signed-off-by: Simon Glass <sjg@chromium.org>
These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.
Signed-off-by: Simon Glass <sjg@chromium.org>
This seems pretty old now. It has not been converted to driver model and
is not used by any boards.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch add mmc and sd support for Mediatek MT7622 SoCs
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
This patch add power domain support for Mediatek MT7622 SoCs
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
This patch fix clock-rate overflow problem in mediatek
clock driver common part.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Due to the pinctrl hardware of MT7622 is difference from others
SoC which using the common part of mediatek pinctrl.
So we need to modify the common part of mediatek pinctrl.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
If make the ref clock optional, no need refer to fixed-clock when
the ref clock is always on or comes from oscillator directly.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
No need check -ENOSYS anymore after add dummy_enable() for
fixed-clock.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
This is used to avoid clk_enable() return -ENOSYS.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Sometimes we may need get (optional) clock without a device,
that means use ofnode.
e.g. when the phy node has subnode, and there is no device created
for subnode, in this case, we need these new APIs to get subnode's
clock.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Add valid check for clk->dev, it's useful when get optional
clock even when the clk point is valid, but its dev will be
NULL.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
If skip all return error number, it may skip some real error cases,
so only skip the error when the clock is not provided in DTS
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
The SSUSB IP's clocks come from ssusbsys module on mt7629,
so add its driver
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
For CMD21 tuning data, the 128/64 bytes data may coming in very
short time, before msdc_start_data(), the read data has already
come, in this case, clear MSDC_INT will cause the interrupt disappear
and lead to the thread hang.
the solution is just clear all interrupts before command was sent.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
This patch adds mmc support for MediaTek MT8512/MT8110 SoCs.
MT8512/MT8110 SoCs puts the tune register at top layer, so
need add new code to support it.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
It was observed (on ClearFog Base) that sending MMC APP_CMD returned
an error on the first attempt. The issue appears to be timing related
since even inserting a puts() short debug entry before the execution
added sufficient delay to receive success on first attempt.
Follow the existing quirks pattern to retry if initial issuance
failed so as to not introduce any delay unless needed.
Signed-off-by: Joel Johnson <mrjoel@lixil.net>
The eSDHC reference clocks should be provided by speed.c in arch/.
And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to
select which clock to use. Because we can make the driver to select
the periperhal clock which is better (provides higher frequency)
automatically if its value is provided by speed.c.
This patch is to drop this option and make driver to select clock
automatically. Also fix peripheral clock calculation issue in
fsl_lsch2_speed.c/fsl_lsch3_speed.c.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The fdt fixup for properties "peripheral-frequency" and "adapter-type"
was once for a Freescale SDK release. The properties haven't been existed
in linux mainline. Drop these useless code.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Some features implicitly depended on MALLOC_F and OF_LIBFDT and would
fail at link-time if these features were not enabled.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMA. This allows to use
macros such as CONFIG_IS_ENABLED() that allow conditional compilation of
code for SPL and U-Boot.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add compatible "fsl,imxrt-usdhc" to make mmc working on i.MXRT platforms
with CONFIG_DM_MMC=y.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Not all architectures(i.e. i.MXRT) support mxc_get_clock() and use DM_CLK
instead. So building could result in failure due to missing
mxc_get_clock().
Make if(CONFIG_IS_ENABLED(CLK)) an #if statement.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Add i.MXRT compatible string and cpu type support to lpuart driver,
to use little endian 32 bits configurations.
Also according to RM, the Receive RX FIFO Enable (RXFE) field in LPUART
FIFO register is bit 3, so this definition should change to 0x08 as done
for i.MX8. It needs also to set baudrate the same way as i.MX8 does.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
This driver assumes that lpuart clock is already enabled before probing
but using DM only lpuart won't be automatically enabled so add
clk_enable() when probing if CONFIG_CLK is defined. If clock is not
found, because DM is not used, let's emit a warning and proceed, because
serial clock could also be already enabled by non DM code. If clock is
found but cna't be enabled then return with error.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping
generic enable()/disable(). Add a different driver because ops are
different respect to GENERIC/USB.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Before set_rate() pllv3 needs enable() to power the pll up.
Add enable() taking into account different power_bit and
different powerup_set, because some pll needs its power_bit to be
set or reset to be powered on.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
div_mask is different for GENERIC and USB pll, so set it according.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Better to register the 2 clock as 2 different drivers because they work
slightly differently depending on power_bit and powerup_set bits coming
on next patches.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
When no GPIO is used to read the card detect status the following
error is seen:
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... MMC: no card present
*** Warning - No block device, using default environment
Fix it by handling the "broken-cd" property in the same way
that drivers/mmc/sdhci.c does, which considers that the SD card
is present when the "broken-cd" property is passed.
Tested on a imx6ul-evk board.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Remove probe function dm_scan_fdt_dev from zynqmp-firmware driver.
It is just binding its subnode zynqmp-clk.
As a result one extra node is showing up in dm tree.
This is not required, it is anyway bound from it's own zynqmp-clk driver.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove hardcoded base addresses of smc controller and nand controller.
Get those addresses from dt and replace wherever they are used.
Remove smc and nand base address from header file too.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When two instances of AXI QSPI with flash are added and tested
simultaneously the spi driver operations are relocated twice.
As a result code is accessing addresses outside of RAM when
relocated second time which is causing a crash.
Tested on Microblaze.
Similar change was done in past by:
commit f238b3f0fb ("watchdog: dm: Support manual relocation for watchdogs")
commit 2588f2ddfd ("dm: sf: Add support for all targets which requires MANUAL_RELOC")
commit 1b4c2aa25b ("gpio: dm: Support manual relocation for gpio")
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove hardcoded base address of nand and replace it with the
value taken from device tree. Remove base address from header
file too.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Make changes to arasan nand driver to move it to driver model.
Select DM_MTD if arasan nand driver is selected.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
DS3232 is an i2c RTC with 236 bytes of battery-backed SRAM.
Add an RTC driver for DS3232 device, which provides time and
date support. Also read and write functions are provided,
which can be used to access the SRAM memory.
Signed-off-by: Nandor Han <nandor.han@vaisala.com>
This driver allows the use of i2c eeprom device or partition as backing
store for boot counter values with DM enabled.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Add specific dm code, but maintaining this driver as is, so more in the
shape of a mii library. Can be moved to dm in a further step.
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
This pull request provides:
* support for FIT images for UEFI binaries
* drivers for hardware random number generators
* an implementation of the EFI_RNG_PROTOCOL
* a sub-command for efidebug to display configuration tables
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAl4UvR4ACgkQxIHbvCwF
GsRJZhAAmlsRBUS3fvFV5GtB8bkWcSU4/s3TVYJui0fOhY02ZDIKkrubZzDx/Lgv
9OaVwjQ3JSmq5XkDmXqzNDzYkxitQ5Qf/cFiBF5HpA3USkOttb3GIfgj0qD6DGzM
cKyhgJm7bZoMN/mkIzkWsry1ASwYpB3ipyoJAfRfryw9ok4j9RfJ7pPieeycGWGJ
0sZsJI0v7e6xt5Qsytk5sZNvlCFhyhl2OMYliAlRKBryh31Ahr2e6KEwsJh7VyCP
4K12eBTqIJq1qHk7Lr0g1CnMCdeOT8J7qvX1+kvt3HupxTMkYRv2AR5CQWRKck5E
RsmcKmiTHz/76w6Gk7kLan7y0UCSHnfHQ3aSEkkx4O/v4OC85VteyLAEriS7J9Hx
xSNyoj01U2wG3SLrUjkAZv6JgyC8uCezRzOHOqN25Q2mRROVq781mcMfRXwdq6cD
L4rrTsIDPzNF19wDa7P5tK6JMF8BDifLNuMTQj5LdJYMHJTJZBWG/vTNFPEldaIP
D9RPoCibTolpiuCYneeXJURHGm5yme7KoxAPiMU+fAWO1F6SO25zxYA7MAiY4OYw
zk7Ipaat0luIu1gC2ICYxrLnsMBq9glABrdq99i0DpUg9n9N/7SpcJSj2DMrFGmY
u4yenWM1KTgjLoVHRhpTbCzF15GlYN4SHXV5iYO+Pof5WQYnv8w=
=SjPV
-----END PGP SIGNATURE-----
Merge tag 'efi-2020-04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-04-rc1
This pull request provides:
* support for FIT images for UEFI binaries
* drivers for hardware random number generators
* an implementation of the EFI_RNG_PROTOCOL
* a sub-command for efidebug to display configuration tables
- Various fixups for amlogic boards
- Unnecessary header includes drop into video/meson
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAl4V0PgACgkQd9zb2sjI
SdEuPw//c0APhovWXXCsRckccBF8SK3WRsVcj5M36g7WXVdUo+MXaPzDUEyDAMfU
xS51FaN7lJJ7ntxEvJ3loFDYh0WrYoanCW+9KxMnJ0GVTdWg6nL0u4yq4exD9f4d
N9Tv8NaN0y2Jn97Y3L70qlutVJjTzUd1oRKWmGDESvXj3+WrJdffEL0uBrCcbmF/
kyEQ3RiDuGhfNrC/mSdhQFG2kmeQc43+Fb1OYq8Wm28zwtYvZuJpdn7FTtwGQk0+
iCjIUN0RKcD+HedJVxHmSnOOTehydk6xQX9215ebo/tTz+WtoqXrFPjEr1mgAhRV
ojEdJcEKAFGwTYuRDmeO6lwAv+k0fkF4drGi7uAOQa3JwD90aKgR0Ig80CzVq1vW
m79WDHFbaQnpIGf94kONF8X0M9nWN9/XYmpJe6KuQaO7YEsIIBsbFP657pJp1J1m
xfwzl2xlx7yaDeR8xv4/N67REuSF/ILeJA0tykkm7NEWkkBrz1d+dXiOaTceY/Wu
z7s3QGpHINMOzuxMZKEZazt+0KQ4UlbAxYRQU3oNRkW3WaCoGimpbjC9FJa4FpoA
Cx2PBRunzx8rK87ZS/X7VUa2v454MSkCGwpmqP+PrekoL2rsRNx/3gWHpzb+Z7E/
nAd0uukYy/WSlzv6bfpRdemQi27gSvDnERf4dj/4kiAiMoKkeiA=
=rkHZ
-----END PGP SIGNATURE-----
Merge tag 'u-boot-amlogic-20200108' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- Khadas VIM3L based on Amlogic S905D3 support
- Various fixups for amlogic boards
- Unnecessary header includes drop into video/meson
In the initialization of sata driver, we want to initialize all port
probes, Therefore, any detection failure between of them should continue
initialization by skipping the current port instead of exit.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
In the initialization of sata driver, we want to initialize all port
probes, Therefore, any detection failure between of them should continue
initialization by skipping the current port instead of exit.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
PCA9450 PMIC series is used to support iMX8MM (PCA9450A) and
iMX8MN (PCA9450B). Add the PMIC driver for both PCA9450A and PCA9450B.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MP use similar ocotp as i.MX8MN, but has changed fuse banks
and ctrl register bit definitions, so update to reflect that.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The current mpc83xx_clk driver is broken for any board for which
mpc83xx_has_pci() is true, i.e. anything not MPC8308:
When is_clk_valid() reports that MPC83XX_CLK_PCI is valid,
init_all_clks() proceeds to call init_single_clk(), but that doesn't
know about either MPC83XX_CLK_PCI or has any handling of the
TYPE_SCCR_ONOFF mode correctly returned by retrieve_mode(). Hence
init_single_clk() ends up returning -EINVAL, and the whole board hangs
in serial_init().
The quickest fix is to simply pretend that clock is invalid for
all, since nobody can have been relying on it. Adding proper support
seems to be a bit more involved than just handling TYPE_SCCR_ONOFF:
- The power-on-reset value of SCCR[PCICM] is 0, so
mpc83xx_clk_enable() would probably need to be tought to enable the
clock.
- The frequency of PCI_SYNC_OUT is either SYS_CLK_IN or SYS_CLK_IN/2
depending on the CFG_CLKIN_DIV configuration input, but that can't
be read from software, so to properly fill out
->speed[MPC83XX_CLK_PCI] I think one would need guidance from
Kconfig or dtb.
Partially fixes: 07d538d281 clk: Add MPC83xx clock driver
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
This adds a message to lists_bind_fdt when it skips initializing a device
pre-relocation. I've had a couple errors where a device didn't initialize
properly because one of its dependencies was missing.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we only support two phases where devres can be used:
bind and probe. This is handled with a boolean. We want to add a new
phase (platdata), so change this to an enum.
Signed-off-by: Simon Glass <sjg@chromium.org>
The devres functionality has very few users in U-Boot, but it still should
have tests. Add a few basic tests of the main functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present when CONFIG_DEBUG_DEVRES is enabled, U-Boot prints log messages
to the console with every devres allocation/free event. This causes most
tests to fail since the console output is not as expected.
In particular this prevents us from adding a device to sandbox which uses
devres in its bind method.
Move devres over to use U-Boot's logging feature instead, and add a new
category for devres.
Signed-off-by: Simon Glass <sjg@chromium.org>
We want to avoid allocating platform data twice. This could happen if
device_probe() is called after device_ofdata_to_platdata() for the same
device.
Add a flag to track whether device_ofdata_to_platdata() has been called on
a device. Check the flag to make sure it doesn't happen twice, and clear
the flag when the data is freed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new internal function, device_ofdata_to_platdata() to handle
allocating private space associated with each device and reading the
platform data from the device tree.
Call this new function from device_probe().
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the parent is probed before the child's ofdata_to_platdata()
method is called. Adjust the logic slightly so that probing parents is
not done until afterwards.
Signed-off-by: Simon Glass <sjg@chromium.org>
This method is supposed to extract platform data from the device tree. It
should be done before the device itself is probed. Move it earlier in the
device_probe() function.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the clock driver reads its ofdata in the probe() method. This
is not correct although it is often harmless.
However in this case it causes a problem, something like this:
- ast_get_scu() is called (from somewhere) to get the SCI address
- this probes the clock
- first sets up ofdata (which does nothing at present)
- DM marks clock device as active
- DM calls pinctrl
- pinctrl probes and calls ast_get_scu() in ast2500_pinctrl_probe()
- ast_get_scu() probes the clock, but sees it already marked as
probed
- ast_get_scu() accesses the clock's private data, with scu as NULL
- DM calls clock probe function ast2500_clk_probe() which reads scu
By putting the read of scu into the correct method, scu is read as part of
ofdata setup, and everything is OK.
Note: This problem did not matter until now since DM always probed all
parents before reading a child's ofdata. The fact that pinctrl is a child
of clock seems to trigger this strange bug.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
