Commit Graph

13 Commits

Author SHA1 Message Date
Michal Simek
f5a122e2ab ARM: zynq: Change zc770 xm011 Nand x16 configurations
Instead of symlink include origin file and just change model description.
Difference is not in DT but in ps7_init configurations which is taken based
on device tree name that's why the same DT can't be used.

Also update model and update comments to match configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06 12:51:31 +02:00
Michal Simek
4cd8bf47ed ARM: zynq: Add missing nand/smcc nodes
Add missing nand/smcc description.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14 09:05:55 +01:00
Luis Araneda
9896dc6558 ARM: dts: zynq: correct and improve the model property of dt files
Replace the current value of the model property by a more accurate
description of each board (which includes the manufacturer), as some
of the boards had the same value ("Xilinx Zynq")

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:00 +01:00
Michal Simek
99a2e34d77 arm: zynq: Fix eeprom dt nodes
- Use eeprom for node name
- Use atmel compatible string instead of at.
- Add missing labels

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09 12:14:49 +02:00
Michal Simek
051a8ad7bb arm: zynq: Sync up licenses with mainline kernel
Use different location for SPDX line. Also update dates for new mainline
DTS files.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09 12:14:49 +02:00
Michal Simek
cc7978bef9 ARM: zynq: Remove DTC 1.4.2 warnings
DTC 1.4.2 reports these warnings:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name
Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property,
but no unit name
Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name,
but no reg property

This patch is fixing them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:38 +01:00
Michal Simek
b347c14426 ARM: zynq: Create empty line below headers
Sync with others zynq DTS files.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:02 +02:00
Michal Simek
936bbc5d16 ARM: zynq: Fix bootargs in board dtsi
- Sync with Linux kernel
- Remove rootfs
- Remove earlyprintk

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:01 +02:00
Michal Simek
7ebf67a34c ARM: zynq: Move spi node to aligned location
Keep nodes aligned.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:55 +01:00
Michal Simek
4691941b45 ARM: zynq: Fix all remaining zynq platform to use stdout-path
Fix console setup for all remaining zynq boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:55 +01:00
Simon Glass
035c6b271d arm: zynq: dts: Add U-Boot device tree additions
We need to mark some device tree nodes so that they are available before
relocation. This enables driver model to find these automatically. In the
case of SPL it ensures that these nodes will be retained in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-04 14:49:53 +01:00
Michal Simek
f0600af212 ARM: dts: Rename memory@0 to memory
zynq-7000.dtsi include skeleton.dtsi which contains memory node with
base address and size zero. If you add memory@0 node to the platform DTS
in final DTB there are two memory nodes and U-Boot works with the first
one (with zeros) which end up in failing in dram_init because size is
zero.
Platform memory node should rewrite default memory node setup from
skeleton.dtsi that's why platfroms needs to also use memory as node name
instead of memory@0.

Reported-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-08-19 11:28:15 +02:00
Michal Simek
6d6e3dbefe ARM: zynq: Add support for zc770-xm011
Add xm011 DTS file and related configs and configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:26 +02:00