Commit Graph

7 Commits

Author SHA1 Message Date
Simon Glass
41575d8e4c dm: treewide: Rename auto_alloc_size members to be shorter
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 08:00:25 -07:00
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Jagan Teki
82111469a5 clk: sunxi: Implement SPI clocks, resets
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all
  supported Allwinner SoCs
- Implement SPI resets via ccu_reset for all supported
  Allwinner SoCs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-04 18:08:56 +05:30
Andre Przywara
bb3e5aa289 sunxi: clk: add MMC gates/resets
Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.

We don't advertise the mod clock yet, as this is still handled by the
MMC driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: add V3S, A80 gates/resets]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:30:11 +05:30
Jagan Teki
8606f960d4 clk: sunxi: Implement UART resets
Implement UART resets for all relevant Allwinner SoC
clock drivers via ccu reset table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
4acc711930 clk: sunxi: Implement UART clocks
Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
3ab029368a clk: sunxi: Add Allwinner A23/A33 CLK driver
Add initial clock driver for Allwinner A23/A33.

- Implement USB bus and USB clocks via ccu_clk_gate table
  for A23/A33, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for A23/A33, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30