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stm32f4: add cpu clock option for 180 MHz
While most stm32f4 run at 168 MHz, stm32f429 can work till 180 MHz. Add option to select 180 MHz through macro CONFIG_SYS_CLK_FREQ. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> To: Albert Aribaud <albert.u.boot@aribaud.net> To: Tom Rini <trini@konsulko.com> To: Kamil Lulko <rev13@wp.pl> Cc: u-boot@lists.denx.de
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@ -92,7 +92,20 @@ struct pll_psc {
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#error "CONFIG_STM32_HSE_HZ not defined!"
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#error "CONFIG_STM32_HSE_HZ not defined!"
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#else
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#else
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#if (CONFIG_STM32_HSE_HZ == 8000000)
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#if (CONFIG_STM32_HSE_HZ == 8000000)
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struct pll_psc pll_psc_168 = {
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#if (CONFIG_SYS_CLK_FREQ == 180000000)
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/* 180 MHz */
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struct pll_psc sys_pll_psc = {
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.pll_m = 8,
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.pll_n = 360,
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.pll_p = 2,
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.pll_q = 8,
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.ahb_psc = AHB_PSC_1,
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.apb1_psc = APB_PSC_4,
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.apb2_psc = APB_PSC_2
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};
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#else
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/* default 168 MHz */
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struct pll_psc sys_pll_psc = {
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.pll_m = 8,
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.pll_m = 8,
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.pll_n = 336,
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.pll_n = 336,
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.pll_p = 2,
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.pll_p = 2,
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@ -101,6 +114,7 @@ struct pll_psc pll_psc_168 = {
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.apb1_psc = APB_PSC_4,
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.apb1_psc = APB_PSC_4,
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.apb2_psc = APB_PSC_2
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.apb2_psc = APB_PSC_2
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};
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};
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#endif
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#else
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#else
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#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
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#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
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#endif
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#endif
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@ -122,19 +136,19 @@ int configure_clocks(void)
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while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
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while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
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;
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;
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/* Enable high performance mode, System frequency up to 168 MHz */
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/* Enable high performance mode, System frequency up to 180 MHz */
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setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
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setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
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writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
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writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
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setbits_le32(&STM32_RCC->cfgr, ((
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setbits_le32(&STM32_RCC->cfgr, ((
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pll_psc_168.ahb_psc << RCC_CFGR_HPRE_SHIFT)
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sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
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| (pll_psc_168.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
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| (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
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| (pll_psc_168.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
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| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
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writel(pll_psc_168.pll_m
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writel(sys_pll_psc.pll_m
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| (pll_psc_168.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
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| (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
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| (((pll_psc_168.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
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| (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
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| (pll_psc_168.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
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| (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
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&STM32_RCC->pllcfgr);
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&STM32_RCC->pllcfgr);
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setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
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setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
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