mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
ARM: dts: stm32: split sdram pin & timing parameter into specific board dts
As different boards has their own sdram hw connection, mount different sdram modules, so move sdram timing parameter and pin configuration to their board device tree. Signed-off-by: dillon min <dillon.minfei@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
dillon min
Patrice Chotard
parent
b46dd116ce
commit
ffca1967ed
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@ -20,6 +20,7 @@
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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mmc0 = &sdmmc1;
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pinctrl0 = &pinctrl;
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};
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soc {
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@ -36,30 +37,6 @@
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pinctrl-0 = <&fmc_pins>;
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pinctrl-names = "default";
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status = "okay";
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/*
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* Memory configuration from sdram datasheet IS42S32800G-6BLI
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* first bank is bank@0
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* second bank is bank@1
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*/
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bank1: bank@1 {
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st,sdram-control = /bits/ 8 <NO_COL_9
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NO_ROW_12
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MWIDTH_32
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BANKS_4
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CAS_2
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SDCLK_3
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RD_BURST_EN
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RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_1
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TXSR_1
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TRAS_1
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TRC_6
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TRP_2
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TWR_1
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TRCD_1>;
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st,sdram-refcount = <1539>;
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};
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};
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};
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};
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@ -136,77 +113,6 @@
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compatible = "st,stm32-gpio";
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};
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&pinctrl {
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fmc_pins: fmc@0 {
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pins {
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pinmux = <STM32_PINMUX('D', 0, AF12)>,
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<STM32_PINMUX('D', 1, AF12)>,
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<STM32_PINMUX('D', 8, AF12)>,
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<STM32_PINMUX('D', 9, AF12)>,
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<STM32_PINMUX('D',10, AF12)>,
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<STM32_PINMUX('D',14, AF12)>,
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<STM32_PINMUX('D',15, AF12)>,
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<STM32_PINMUX('E', 0, AF12)>,
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<STM32_PINMUX('E', 1, AF12)>,
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<STM32_PINMUX('E', 7, AF12)>,
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<STM32_PINMUX('E', 8, AF12)>,
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<STM32_PINMUX('E', 9, AF12)>,
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<STM32_PINMUX('E',10, AF12)>,
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<STM32_PINMUX('E',11, AF12)>,
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<STM32_PINMUX('E',12, AF12)>,
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<STM32_PINMUX('E',13, AF12)>,
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<STM32_PINMUX('E',14, AF12)>,
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<STM32_PINMUX('E',15, AF12)>,
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<STM32_PINMUX('F', 0, AF12)>,
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<STM32_PINMUX('F', 1, AF12)>,
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<STM32_PINMUX('F', 2, AF12)>,
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<STM32_PINMUX('F', 3, AF12)>,
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<STM32_PINMUX('F', 4, AF12)>,
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<STM32_PINMUX('F', 5, AF12)>,
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<STM32_PINMUX('F',11, AF12)>,
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<STM32_PINMUX('F',12, AF12)>,
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<STM32_PINMUX('F',13, AF12)>,
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<STM32_PINMUX('F',14, AF12)>,
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<STM32_PINMUX('F',15, AF12)>,
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<STM32_PINMUX('G', 0, AF12)>,
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<STM32_PINMUX('G', 1, AF12)>,
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<STM32_PINMUX('G', 2, AF12)>,
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<STM32_PINMUX('G', 4, AF12)>,
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<STM32_PINMUX('G', 5, AF12)>,
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<STM32_PINMUX('G', 8, AF12)>,
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<STM32_PINMUX('G',15, AF12)>,
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<STM32_PINMUX('H', 5, AF12)>,
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<STM32_PINMUX('H', 6, AF12)>,
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<STM32_PINMUX('H', 7, AF12)>,
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<STM32_PINMUX('H', 8, AF12)>,
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<STM32_PINMUX('H', 9, AF12)>,
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<STM32_PINMUX('H',10, AF12)>,
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<STM32_PINMUX('H',11, AF12)>,
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<STM32_PINMUX('H',12, AF12)>,
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<STM32_PINMUX('H',13, AF12)>,
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<STM32_PINMUX('H',14, AF12)>,
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<STM32_PINMUX('H',15, AF12)>,
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<STM32_PINMUX('I', 0, AF12)>,
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<STM32_PINMUX('I', 1, AF12)>,
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<STM32_PINMUX('I', 2, AF12)>,
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<STM32_PINMUX('I', 3, AF12)>,
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<STM32_PINMUX('I', 4, AF12)>,
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<STM32_PINMUX('I', 5, AF12)>,
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<STM32_PINMUX('I', 6, AF12)>,
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<STM32_PINMUX('I', 7, AF12)>,
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<STM32_PINMUX('I', 9, AF12)>,
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<STM32_PINMUX('I',10, AF12)>;
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slew-rate = <3>;
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};
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};
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};
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&pwrcfg {
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u-boot,dm-pre-reloc;
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};
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@ -222,3 +128,7 @@
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&timer5 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl {
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u-boot,dm-pre-reloc;
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};
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@ -1,3 +1,101 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <stm32h7-u-boot.dtsi>
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&fmc {
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/*
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* Memory configuration from sdram datasheet IS42S32800G-6BLI
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* first bank is bank@0
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* second bank is bank@1
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*/
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bank1: bank@1 {
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st,sdram-control = /bits/ 8 <NO_COL_9
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NO_ROW_12
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MWIDTH_32
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BANKS_4
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CAS_2
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SDCLK_3
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RD_BURST_EN
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RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_1
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TXSR_1
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TRAS_1
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TRC_6
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TRP_2
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TWR_1
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TRCD_1>;
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st,sdram-refcount = <1539>;
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};
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};
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&pinctrl {
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fmc_pins: fmc@0 {
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pins {
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pinmux = <STM32_PINMUX('D', 0, AF12)>,
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<STM32_PINMUX('D', 1, AF12)>,
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<STM32_PINMUX('D', 8, AF12)>,
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<STM32_PINMUX('D', 9, AF12)>,
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<STM32_PINMUX('D',10, AF12)>,
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<STM32_PINMUX('D',14, AF12)>,
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<STM32_PINMUX('D',15, AF12)>,
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<STM32_PINMUX('E', 0, AF12)>,
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<STM32_PINMUX('E', 1, AF12)>,
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<STM32_PINMUX('E', 7, AF12)>,
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<STM32_PINMUX('E', 8, AF12)>,
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<STM32_PINMUX('E', 9, AF12)>,
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<STM32_PINMUX('E',10, AF12)>,
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<STM32_PINMUX('E',11, AF12)>,
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<STM32_PINMUX('E',12, AF12)>,
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<STM32_PINMUX('E',13, AF12)>,
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<STM32_PINMUX('E',14, AF12)>,
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<STM32_PINMUX('E',15, AF12)>,
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<STM32_PINMUX('F', 0, AF12)>,
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<STM32_PINMUX('F', 1, AF12)>,
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<STM32_PINMUX('F', 2, AF12)>,
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<STM32_PINMUX('F', 3, AF12)>,
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<STM32_PINMUX('F', 4, AF12)>,
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<STM32_PINMUX('F', 5, AF12)>,
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<STM32_PINMUX('F',11, AF12)>,
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<STM32_PINMUX('F',12, AF12)>,
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<STM32_PINMUX('F',13, AF12)>,
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<STM32_PINMUX('F',14, AF12)>,
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<STM32_PINMUX('F',15, AF12)>,
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<STM32_PINMUX('G', 0, AF12)>,
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<STM32_PINMUX('G', 1, AF12)>,
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<STM32_PINMUX('G', 2, AF12)>,
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<STM32_PINMUX('G', 4, AF12)>,
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<STM32_PINMUX('G', 5, AF12)>,
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<STM32_PINMUX('G', 8, AF12)>,
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<STM32_PINMUX('G',15, AF12)>,
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<STM32_PINMUX('H', 5, AF12)>,
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<STM32_PINMUX('H', 6, AF12)>,
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<STM32_PINMUX('H', 7, AF12)>,
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<STM32_PINMUX('H', 8, AF12)>,
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<STM32_PINMUX('H', 9, AF12)>,
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<STM32_PINMUX('H',10, AF12)>,
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<STM32_PINMUX('H',11, AF12)>,
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<STM32_PINMUX('H',12, AF12)>,
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<STM32_PINMUX('H',13, AF12)>,
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<STM32_PINMUX('H',14, AF12)>,
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<STM32_PINMUX('H',15, AF12)>,
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<STM32_PINMUX('I', 0, AF12)>,
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<STM32_PINMUX('I', 1, AF12)>,
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<STM32_PINMUX('I', 2, AF12)>,
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<STM32_PINMUX('I', 3, AF12)>,
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<STM32_PINMUX('I', 4, AF12)>,
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<STM32_PINMUX('I', 5, AF12)>,
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<STM32_PINMUX('I', 6, AF12)>,
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<STM32_PINMUX('I', 7, AF12)>,
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<STM32_PINMUX('I', 9, AF12)>,
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<STM32_PINMUX('I',10, AF12)>;
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slew-rate = <3>;
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};
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};
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};
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@ -1,3 +1,101 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <stm32h7-u-boot.dtsi>
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&fmc {
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/*
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* Memory configuration from sdram datasheet IS42S32800G-6BLI
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* first bank is bank@0
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* second bank is bank@1
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*/
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bank1: bank@1 {
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st,sdram-control = /bits/ 8 <NO_COL_9
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NO_ROW_12
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MWIDTH_32
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BANKS_4
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CAS_2
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SDCLK_3
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RD_BURST_EN
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RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_1
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TXSR_1
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TRAS_1
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TRC_6
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TRP_2
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TWR_1
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TRCD_1>;
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st,sdram-refcount = <1539>;
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};
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};
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&pinctrl {
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fmc_pins: fmc@0 {
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pins {
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pinmux = <STM32_PINMUX('D', 0, AF12)>,
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<STM32_PINMUX('D', 1, AF12)>,
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<STM32_PINMUX('D', 8, AF12)>,
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<STM32_PINMUX('D', 9, AF12)>,
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<STM32_PINMUX('D',10, AF12)>,
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<STM32_PINMUX('D',14, AF12)>,
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<STM32_PINMUX('D',15, AF12)>,
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<STM32_PINMUX('E', 0, AF12)>,
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<STM32_PINMUX('E', 1, AF12)>,
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<STM32_PINMUX('E', 7, AF12)>,
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<STM32_PINMUX('E', 8, AF12)>,
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<STM32_PINMUX('E', 9, AF12)>,
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<STM32_PINMUX('E',10, AF12)>,
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<STM32_PINMUX('E',11, AF12)>,
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<STM32_PINMUX('E',12, AF12)>,
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<STM32_PINMUX('E',13, AF12)>,
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<STM32_PINMUX('E',14, AF12)>,
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<STM32_PINMUX('E',15, AF12)>,
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<STM32_PINMUX('F', 0, AF12)>,
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<STM32_PINMUX('F', 1, AF12)>,
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<STM32_PINMUX('F', 2, AF12)>,
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<STM32_PINMUX('F', 3, AF12)>,
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<STM32_PINMUX('F', 4, AF12)>,
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<STM32_PINMUX('F', 5, AF12)>,
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<STM32_PINMUX('F',11, AF12)>,
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<STM32_PINMUX('F',12, AF12)>,
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<STM32_PINMUX('F',13, AF12)>,
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<STM32_PINMUX('F',14, AF12)>,
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<STM32_PINMUX('F',15, AF12)>,
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<STM32_PINMUX('G', 0, AF12)>,
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<STM32_PINMUX('G', 1, AF12)>,
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<STM32_PINMUX('G', 2, AF12)>,
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<STM32_PINMUX('G', 4, AF12)>,
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<STM32_PINMUX('G', 5, AF12)>,
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<STM32_PINMUX('G', 8, AF12)>,
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<STM32_PINMUX('G',15, AF12)>,
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<STM32_PINMUX('H', 5, AF12)>,
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<STM32_PINMUX('H', 6, AF12)>,
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<STM32_PINMUX('H', 7, AF12)>,
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<STM32_PINMUX('H', 8, AF12)>,
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<STM32_PINMUX('H', 9, AF12)>,
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<STM32_PINMUX('H',10, AF12)>,
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<STM32_PINMUX('H',11, AF12)>,
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<STM32_PINMUX('H',12, AF12)>,
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<STM32_PINMUX('H',13, AF12)>,
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<STM32_PINMUX('H',14, AF12)>,
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<STM32_PINMUX('H',15, AF12)>,
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<STM32_PINMUX('I', 0, AF12)>,
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<STM32_PINMUX('I', 1, AF12)>,
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<STM32_PINMUX('I', 2, AF12)>,
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<STM32_PINMUX('I', 3, AF12)>,
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<STM32_PINMUX('I', 4, AF12)>,
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<STM32_PINMUX('I', 5, AF12)>,
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<STM32_PINMUX('I', 6, AF12)>,
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<STM32_PINMUX('I', 7, AF12)>,
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<STM32_PINMUX('I', 9, AF12)>,
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<STM32_PINMUX('I',10, AF12)>;
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slew-rate = <3>;
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};
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};
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};
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