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Merge branch 'master' of git://git.denx.de/u-boot-socfpga

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This commit is contained in:
Tom Rini 2018-07-26 11:43:26 -04:00
commit ff6bef4852
4 changed files with 19 additions and 4 deletions
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2
arch/arm/Kconfig
View File

@ -766,6 +766,7 @@ config ARCH_SOCFPGA
select DM_SERIAL
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
select SPL_DM_RESET if DM_RESET
select SPL_LIBCOMMON_SUPPORT
select SPL_LIBDISK_SUPPORT
select SPL_LIBGENERIC_SUPPORT
@ -774,7 +775,6 @@ config ARCH_SOCFPGA
select SPL_OF_CONTROL
select SPL_SERIAL_SUPPORT
select SPL_DM_SERIAL
select SPL_RESET_SUPPORT
select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT
select SPL_SPI_SUPPORT if DM_SPI
select SPL_WATCHDOG_SUPPORT

4
arch/arm/dts/socfpga_arria10.dtsi
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@ -637,8 +637,8 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
reg = <0xffb90000 0x72000>,
<0xffb80000 0x10000>;
reg = <0xffb90000 0x20>,
<0xffb80000 0x1000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0 99 4>;
dma-mask = <0xffffffff>;

4
arch/arm/mach-socfpga/board.c
View File

@ -21,12 +21,14 @@ DECLARE_GLOBAL_DATA_PTR;
void s_init(void) {
#ifndef CONFIG_ARM64
/*
* Preconfigure ACTLR, make sure Write Full Line of Zeroes is disabled.
* Preconfigure ACTLR and CPACR, make sure Write Full Line of Zeroes
* is disabled in ACTLR.
* This is optional on CycloneV / ArriaV.
* This is mandatory on Arria10, otherwise Linux refuses to boot.
*/
asm volatile(
"mcr p15, 0, %0, c1, c0, 1\n"
"mcr p15, 0, %0, c1, c0, 2\n"
"isb\n"
"dsb\n"
::"r"(0x0));

13
arch/arm/mach-socfpga/misc_arria10.c
View File

@ -93,6 +93,19 @@ static void initialize_security_policies(void)
/* Put OCRAM in non-secure */
writel(0x003f0000, &noc_fw_ocram_base->region0);
writel(0x1, &noc_fw_ocram_base->enable);
/* Put DDR in non-secure */
writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc);
writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS);
/* Enable priviledged and non-priviledged access to L4 peripherals */
writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST);
/* Enable secure and non-secure transactions to bridges */
writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set);
}
int arch_early_init_r(void)