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https://github.com/brain-hackers/u-boot-brain
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ppc4xx: Update PMC440 config file
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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@ -41,7 +41,9 @@
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#define CONFIG_SYS_CLK_FREQ 33333400
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#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
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#define CONFIG_4xx_DCACHE /* enable dcache */
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#endif
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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@ -272,6 +274,7 @@
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CFG_BOOTFILE \
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CFG_ROOTPATH \
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"netdev=eth0\0" \
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"ethrotate=no\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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@ -354,10 +357,6 @@
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#define CONFIG_CMD_SDRAM
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/* POST support */
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/* ethernet POST sometimes freezes the CPU.
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* So disable it for now until issue is solved
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*/
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#if 0
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#define CONFIG_POST (CFG_POST_MEMORY | \
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CFG_POST_CPU | \
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CFG_POST_UART | \
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@ -366,15 +365,6 @@
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CFG_POST_FPU | \
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CFG_POST_ETHER | \
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CFG_POST_SPR)
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#else
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#define CONFIG_POST (CFG_POST_MEMORY | \
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CFG_POST_CPU | \
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CFG_POST_UART | \
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CFG_POST_I2C | \
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CFG_POST_CACHE | \
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CFG_POST_FPU | \
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CFG_POST_SPR)
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#endif
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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