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https://github.com/brain-hackers/u-boot-brain
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clk: divider set rate supporrt
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
parent
1c64330318
commit
fe69b030de
@ -18,6 +18,7 @@
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#include <dm/lists.h>
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#include <dm/device-internal.h>
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#include <linux/clk-provider.h>
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#include <linux/log2.h>
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#include <div64.h>
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#include <clk.h>
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#include "clk.h"
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@ -86,8 +87,95 @@ static ulong clk_divider_recalc_rate(struct clk *clk)
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divider->flags, divider->width);
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}
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static bool _is_valid_table_div(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return true;
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return false;
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}
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static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
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unsigned long flags)
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{
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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return is_power_of_2(div);
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if (table)
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return _is_valid_table_div(table, div);
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return true;
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}
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static unsigned int _get_table_val(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return clkt->val;
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return 0;
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}
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static unsigned int _get_val(const struct clk_div_table *table,
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unsigned int div, unsigned long flags, u8 width)
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{
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if (flags & CLK_DIVIDER_ONE_BASED)
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return div;
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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return __ffs(div);
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if (flags & CLK_DIVIDER_MAX_AT_ZERO)
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return (div == clk_div_mask(width) + 1) ? 0 : div;
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if (table)
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return _get_table_val(table, div);
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return div - 1;
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}
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int divider_get_val(unsigned long rate, unsigned long parent_rate,
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const struct clk_div_table *table, u8 width,
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unsigned long flags)
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{
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unsigned int div, value;
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div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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if (!_is_valid_div(table, div, flags))
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return -EINVAL;
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value = _get_val(table, div, flags, width);
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return min_t(unsigned int, value, clk_div_mask(width));
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}
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static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
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{
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struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
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dev_get_clk_ptr(clk->dev) : clk);
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unsigned long parent_rate = clk_get_parent_rate(clk);
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int value;
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u32 val;
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value = divider_get_val(rate, parent_rate, divider->table,
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divider->width, divider->flags);
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if (value < 0)
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return value;
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if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
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val = clk_div_mask(divider->width) << (divider->shift + 16);
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} else {
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val = readl(divider->reg);
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val &= ~(clk_div_mask(divider->width) << divider->shift);
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}
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val |= (u32)value << divider->shift;
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writel(val, divider->reg);
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return clk_get_rate(clk);
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}
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const struct clk_ops clk_divider_ops = {
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.get_rate = clk_divider_recalc_rate,
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.set_rate = clk_divider_set_rate,
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};
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static struct clk *_register_divider(struct device *dev, const char *name,
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