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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv

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- Fix HiFive Unleashed the broken problem by call fix_fdt() before
  reserve_fdt().  Please refer to
  https://www.mail-archive.com/u-boot@lists.denx.de/msg379444.html for
  master u-boot broken for HiFive Unleashed.
- Add unaligned exception cmd.
- Refine sifive/fu540 spl flow.
- Add  additional crash information for efi.
- Update sipeed/maix doc.
- Two minor refine.
This commit is contained in:
Tom Rini 2020-08-14 08:38:01 -04:00
commit fe5c777df2
14 changed files with 202 additions and 111 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
arch/riscv/cpu/fu540/Kconfig
View File

@ -5,6 +5,9 @@
config SIFIVE_FU540
bool
select ARCH_EARLY_INIT_R
select SUPPORT_SPL
select RAM
select SPL_RAM if SPL
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
@ -13,6 +16,25 @@ config SIFIVE_FU540
imply SPL_CPU_SUPPORT
imply SPL_OPENSBI
imply SPL_LOAD_FIT
imply SMP
imply CLK_SIFIVE
imply CLK_SIFIVE_FU540_PRCI
imply SIFIVE_SERIAL
imply MACB
imply MII
imply SPI
imply SPI_SIFIVE
imply MMC
imply MMC_SPI
imply MMC_BROKEN_CD
imply CMD_MMC
imply DM_GPIO
imply SIFIVE_GPIO
imply CMD_GPIO
imply MISC
imply SIFIVE_OTP
imply DM_PWM
imply PWM_SIFIVE
if ENV_IS_IN_SPI_FLASH

2
arch/riscv/cpu/fu540/cache.c
View File

@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR;
int cache_enable_ways(void)
{
const void *blob = gd->fdt_blob;
int node = (-FDT_ERR_NOTFOUND);
int node;
fdt_addr_t base;
u32 config;
u32 ways;

2
arch/riscv/cpu/fu540/spl.c
View File

@ -7,7 +7,7 @@
#include <dm.h>
#include <log.h>
int soc_spl_init(void)
int spl_soc_init(void)
{
int ret;
struct udevice *dev;

2
arch/riscv/include/asm/arch-fu540/spl.h
View File

@ -9,6 +9,6 @@
#ifndef _SPL_SIFIVE_H
#define _SPL_SIFIVE_H
int soc_spl_init(void);
int spl_soc_init(void);
#endif /* _SPL_SIFIVE_H */

7
arch/riscv/include/asm/spl.h
View File

@ -28,4 +28,11 @@ enum {
BOOT_DEVICE_NONE
};
/**
* spl_board_init_f() - initialize board in the SPL phase
*
* @return 0 if succeeded, -ve on error
*/
int spl_board_init_f(void);
#endif

2
arch/riscv/lib/andes_plic.c
View File

@ -52,7 +52,7 @@ static int init_plic(void)
if (ret)
return ret;
if (ret == 0 && dev) {
if (dev) {
ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
const char *device_type;

57
arch/riscv/lib/interrupts.c
View File

@ -10,36 +10,43 @@
*/
#include <common.h>
#include <efi_loader.h>
#include <hang.h>
#include <irq_func.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/encoding.h>
DECLARE_GLOBAL_DATA_PTR;
static void show_efi_loaded_images(uintptr_t epc)
{
efi_print_image_infos((void *)epc);
}
static void show_regs(struct pt_regs *regs)
{
#ifdef CONFIG_SHOW_REGS
printf("RA: " REG_FMT " SP: " REG_FMT " GP: " REG_FMT "\n",
regs->ra, regs->sp, regs->gp);
printf("TP: " REG_FMT " T0: " REG_FMT " T1: " REG_FMT "\n",
regs->tp, regs->t0, regs->t1);
printf("T2: " REG_FMT " S0: " REG_FMT " S1: " REG_FMT "\n",
regs->t2, regs->s0, regs->s1);
printf("A0: " REG_FMT " A1: " REG_FMT " A2: " REG_FMT "\n",
regs->a0, regs->a1, regs->a2);
printf("A3: " REG_FMT " A4: " REG_FMT " A5: " REG_FMT "\n",
regs->a3, regs->a4, regs->a5);
printf("A6: " REG_FMT " A7: " REG_FMT " S2: " REG_FMT "\n",
regs->a6, regs->a7, regs->s2);
printf("S3: " REG_FMT " S4: " REG_FMT " S5: " REG_FMT "\n",
regs->s3, regs->s4, regs->s5);
printf("S6: " REG_FMT " S7: " REG_FMT " S8: " REG_FMT "\n",
regs->s6, regs->s7, regs->s8);
printf("S9: " REG_FMT " S10: " REG_FMT " S11: " REG_FMT "\n",
regs->s9, regs->s10, regs->s11);
printf("T3: " REG_FMT " T4: " REG_FMT " T5: " REG_FMT "\n",
regs->t3, regs->t4, regs->t5);
printf("T6: " REG_FMT "\n", regs->t6);
printf("SP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n",
regs->sp, regs->gp, regs->tp);
printf("T0: " REG_FMT " T1: " REG_FMT " T2: " REG_FMT "\n",
regs->t0, regs->t1, regs->t2);
printf("S0: " REG_FMT " S1: " REG_FMT " A0: " REG_FMT "\n",
regs->s0, regs->s1, regs->a0);
printf("A1: " REG_FMT " A2: " REG_FMT " A3: " REG_FMT "\n",
regs->a1, regs->a2, regs->a3);
printf("A4: " REG_FMT " A5: " REG_FMT " A6: " REG_FMT "\n",
regs->a4, regs->a5, regs->a6);
printf("A7: " REG_FMT " S2: " REG_FMT " S3: " REG_FMT "\n",
regs->a7, regs->s2, regs->s3);
printf("S4: " REG_FMT " S5: " REG_FMT " S6: " REG_FMT "\n",
regs->s4, regs->s5, regs->s6);
printf("S7: " REG_FMT " S8: " REG_FMT " S9: " REG_FMT "\n",
regs->s7, regs->s8, regs->s9);
printf("S10: " REG_FMT " S11: " REG_FMT " T3: " REG_FMT "\n",
regs->s10, regs->s11, regs->t3);
printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n\n",
regs->t4, regs->t5, regs->t6);
#endif
}
@ -69,8 +76,14 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
else
printf("Unhandled exception code: %ld\n", code);
printf("EPC: " REG_FMT " TVAL: " REG_FMT "\n", epc, tval);
printf("EPC: " REG_FMT " RA: " REG_FMT " TVAL: " REG_FMT "\n",
epc, regs->ra, tval);
if (gd->flags & GD_FLG_RELOC)
printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n\n",
epc - gd->reloc_off, regs->ra - gd->reloc_off);
show_regs(regs);
show_efi_loaded_images(epc);
hang();
}

9
arch/riscv/lib/spl.c
View File

@ -13,6 +13,11 @@
DECLARE_GLOBAL_DATA_PTR;
__weak int spl_board_init_f(void)
{
return 0;
}
__weak void board_init_f(ulong dummy)
{
int ret;
@ -24,6 +29,10 @@ __weak void board_init_f(ulong dummy)
arch_cpu_init_dm();
preloader_console_init();
ret = spl_board_init_f();
if (ret)
panic("spl_board_init_f() failed: %d\n", ret);
}
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)

23
board/sifive/fu540/Kconfig
View File

@ -26,10 +26,7 @@ config SPL_OPENSBI_LOAD_ADDR
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SIFIVE_FU540
select SUPPORT_SPL
select ENV_IS_IN_SPI_FLASH
select RAM
select SPL_RAM if SPL
imply CMD_DHCP
imply CMD_EXT2
imply CMD_EXT4
@ -40,34 +37,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply CMD_NET
imply CMD_PING
imply CMD_SF
imply CLK_SIFIVE
imply CLK_SIFIVE_FU540_PRCI
imply DOS_PARTITION
imply EFI_PARTITION
imply IP_DYN
imply ISO_PARTITION
imply MACB
imply MII
imply NET_RANDOM_ETHADDR
imply PHY_LIB
imply PHY_MSCC
imply SIFIVE_SERIAL
imply SPI
imply SPI_SIFIVE
imply SPI_FLASH
imply SPI_FLASH_ISSI
imply MMC
imply MMC_SPI
imply MMC_BROKEN_CD
imply CMD_MMC
imply DM_GPIO
imply SIFIVE_GPIO
imply CMD_GPIO
imply SMP
imply MISC
imply SIFIVE_OTP
imply DM_PWM
imply PWM_SIFIVE
imply SYSRESET
imply SYSRESET_GPIO

33
board/sifive/fu540/fu540.c
View File

@ -13,7 +13,6 @@
#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <misc.h>
#include <spl.h>
#include <asm/arch/cache.h>
@ -127,35 +126,3 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_SPL
#define MODE_SELECT_REG 0x1000
#define MODE_SELECT_QSPI 0x6
#define MODE_SELECT_SD 0xb
#define MODE_SELECT_MASK GENMASK(3, 0)
u32 spl_boot_device(void)
{
u32 mode_select = readl((void *)MODE_SELECT_REG);
u32 boot_device = mode_select & MODE_SELECT_MASK;
switch (boot_device) {
case MODE_SELECT_QSPI:
return BOOT_DEVICE_SPI;
case MODE_SELECT_SD:
return BOOT_DEVICE_MMC1;
default:
debug("Unsupported boot device 0x%x but trying MMC1\n",
boot_device);
return BOOT_DEVICE_MMC1;
}
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* boot using first FIT config */
return 0;
}
#endif

46
board/sifive/fu540/spl.c
View File

@ -11,17 +11,23 @@
#include <misc.h>
#include <log.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
int init_clk_and_ddr(void)
#define MODE_SELECT_REG 0x1000
#define MODE_SELECT_QSPI 0x6
#define MODE_SELECT_SD 0xb
#define MODE_SELECT_MASK GENMASK(3, 0)
int spl_board_init_f(void)
{
int ret;
ret = soc_spl_init();
ret = spl_soc_init();
if (ret) {
debug("FU540 SPL init failed: %d\n", ret);
return ret;
@ -56,19 +62,27 @@ int init_clk_and_ddr(void)
return 0;
}
void board_init_f(ulong dummy)
u32 spl_boot_device(void)
{
int ret;
u32 mode_select = readl((void *)MODE_SELECT_REG);
u32 boot_device = mode_select & MODE_SELECT_MASK;
ret = spl_early_init();
if (ret)
panic("spl_early_init() failed: %d\n", ret);
arch_cpu_init_dm();
preloader_console_init();
ret = init_clk_and_ddr();
if (ret)
panic("init_clk_and_ddr() failed: %d\n", ret);
switch (boot_device) {
case MODE_SELECT_QSPI:
return BOOT_DEVICE_SPI;
case MODE_SELECT_SD:
return BOOT_DEVICE_MMC1;
default:
debug("Unsupported boot device 0x%x but trying MMC1\n",
boot_device);
return BOOT_DEVICE_MMC1;
}
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* boot using first FIT config */
return 0;
}
#endif

17
cmd/riscv/exception.c
View File

@ -8,6 +8,18 @@
#include <common.h>
#include <command.h>
static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
asm volatile (
"auipc a1, 0\n"
"ori a1, a1, 3\n"
"lw a2, (0)(a1)\n"
);
printf("The system supports unaligned access.\n");
return CMD_RET_SUCCESS;
}
static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@ -16,6 +28,8 @@ static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc,
}
static struct cmd_tbl cmd_sub[] = {
U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned,
"", ""),
U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
"", ""),
};
@ -23,7 +37,8 @@ static struct cmd_tbl cmd_sub[] = {
static char exception_help_text[] =
"<ex>\n"
" The following exceptions are available:\n"
" undefined - undefined instruction\n"
" undefined - illegal instruction\n"
" unaligned - load address misaligned\n"
;
#include <exception.h>

6
common/board_f.c
View File

@ -919,6 +919,9 @@ static const init_fnc_t init_sequence_f[] = {
* - board info struct
*/
setup_dest_addr,
#ifdef CONFIG_OF_BOARD_FIXUP
fix_fdt,
#endif
#ifdef CONFIG_PRAM
reserve_pram,
#endif
@ -941,9 +944,6 @@ static const init_fnc_t init_sequence_f[] = {
INIT_FUNC_WATCHDOG_RESET
setup_bdinfo,
display_new_sp,
#ifdef CONFIG_OF_BOARD_FIXUP
fix_fdt,
#endif
INIT_FUNC_WATCHDOG_RESET
reloc_fdt,
reloc_bootstage,

85
doc/board/sipeed/maix.rst
View File

@ -1,8 +1,8 @@
.. SPDX-License-Identifier: GPL-2.0+
.. Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
Maix Bit
========
MAIX
====
Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor,
a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate
@ -13,8 +13,10 @@ peripherals include 8M of SRAM (accessible with and without caching); remappable
pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller;
and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash;
on-board usb-serial bridges; ports for cameras, displays, and sd cards; and
ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but
the boards are fairly similar.
ESP32 chips.
Currently, only the Sipeed MAIX BiT V2.0 (bitm) and Sipeed MAIXDUINO are
supported, but the boards are fairly similar.
Documentation for Maix boards is available from
`Sipeed's website <http://dl.sipeed.com/MAIX/HDK/>`_.
@ -26,20 +28,42 @@ details are rather lacking, so most technical reference has been taken from the
Build and boot steps
--------------------
To build u-boot, run
To build U-Boot, run
.. code-block:: none
make sipeed_maix_bitm_defconfig
make <defconfig>
make CROSS_COMPILE=<your cross compile prefix>
To flash u-boot to a maix bit, run
To flash U-Boot, run
.. code-block:: none
kflash -tp /dev/<your tty here> -B bit_mic u-boot-dtb.bin
kflash -tp /dev/<your tty here> -B <board_id> u-boot-dtb.bin
Boot output should look like the following:
The board provides two serial devices, e.g.
* /dev/serial/by-id/usb-Kongou_Hikari_Sipeed-Debug_12345678AB-if00-port0
* /dev/serial/by-id/usb-Kongou_Hikari_Sipeed-Debug_12345678AB-if01-port0
Which one is used for flashing depends on the board.
Currently only a small subset of the board features are supported. So we can
use the same default configuration and device tree. In the long run we may need
separate settings.
======================== ========================== ========== ==========
Board defconfig board_id TTY device
======================== ========================== ========== ==========
Sipeed MAIX BiT sipeed_maix_bitm_defconfig bit first
Sipeed MAIX BiT with Mic sipeed_maix_bitm_defconfig bit_mic first
Sipeed MAIXDUINO sipeed_maix_bitm_defconfig maixduino first
Sipeed MAIX GO goE second
Sipeed MAIX ONE DOCK goD first
======================== ========================== ========== ==========
Flashing causes a reboot of the device. Parameter -t specifies that the serial
console shall be opened immediately. Boot output should look like the following:
.. code-block:: none
@ -238,6 +262,49 @@ Boot Sequence
stage.
8. The boot hart jumps to ``0x80000000``.
Debug UART
^^^^^^^^^^
The Debug UART is provided with the following settings::
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_SIFIVE=y
CONFIG_DEBUG_UART_BASE=0x38000000
CONFIG_DEBUG_UART_CLOCK=390000000
Resetting the board
^^^^^^^^^^^^^^^^^^^
The MAIX boards can be reset using the DTR and RTS lines of the serial console.
How the lines are used depends on the specific board. See the code of kflash.py
for details.
This is the reset sequence for the MAXDUINO and MAIX BiT with Mic:
.. code-block:: python
def reset(self):
self.device.setDTR(False)
self.device.setRTS(False)
time.sleep(0.1)
self.device.setDTR(True)
time.sleep(0.1)
self.device.setDTR(False)
time.sleep(0.1)
and this for the MAIX Bit:
.. code-block:: python
def reset(self):
self.device.setDTR(False)
self.device.setRTS(False)
time.sleep(0.1)
self.device.setRTS(True)
time.sleep(0.1)
self.device.setRTS(False)
time.sleep(0.1)
Memory Map
^^^^^^^^^^