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powerpc/85xx: Cleanup some QE related defines
Move some processor specific QE defines into config_mpc85xx.h and use QE_MURAM_SIZE to cleanup some ifdef mess in the QE immap struct. Also fixed up some comment style issues in immap_qe.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala
parent
c39f44dc6f
commit
fdb4dad31e
@ -67,11 +67,17 @@
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define QE_MURAM_SIZE 0x10000UL
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#define MAX_QE_RISC 2
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#define QE_NUM_OF_SNUM 28
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#elif defined(CONFIG_MPC8569)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define QE_MURAM_SIZE 0x20000UL
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#define MAX_QE_RISC 4
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#define QE_NUM_OF_SNUM 46
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#elif defined(CONFIG_MPC8572)
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#define CONFIG_MAX_CPUS 2
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@ -3,7 +3,7 @@
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* The Internal Memory Map for devices with QE on them. This
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* is the superset of all QE devices (8360, etc.).
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*
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* Copyright (c) 2006-2009 Freescale Semiconductor, Inc.
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* Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc.
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* Author: Shlomi Gridih <gridish@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -15,8 +15,19 @@
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#ifndef __IMMAP_QE_H__
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#define __IMMAP_QE_H__
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/* QE I-RAM
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*/
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#ifdef CONFIG_MPC83xx
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#if defined(CONFIG_MPC8360)
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#define QE_MURAM_SIZE 0xc000UL
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#define MAX_QE_RISC 2
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#define QE_NUM_OF_SNUM 28
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#elif defined(CONFIG_MPC832x)
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#define QE_MURAM_SIZE 0x4000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#endif
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#endif
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/* QE I-RAM */
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typedef struct qe_iram {
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u32 iadd; /* I-RAM Address Register */
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u32 idata; /* I-RAM Data Register */
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@ -25,8 +36,7 @@ typedef struct qe_iram {
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u8 res1[0x70];
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} __attribute__ ((packed)) qe_iram_t;
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/* QE Interrupt Controller
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*/
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/* QE Interrupt Controller */
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typedef struct qe_ic {
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u32 qicr;
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u32 qivec;
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@ -49,8 +59,7 @@ typedef struct qe_ic {
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u8 res3[0x1C];
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} __attribute__ ((packed)) qe_ic_t;
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/* Communications Processor
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*/
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/* Communications Processor */
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typedef struct cp_qe {
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u32 cecr; /* QE command register */
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u32 ceccr; /* QE controller configuration register */
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@ -87,8 +96,7 @@ typedef struct cp_qe {
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u8 res13[0x280];
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} __attribute__ ((packed)) cp_qe_t;
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/* QE Multiplexer
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*/
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/* QE Multiplexer */
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typedef struct qe_mux {
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u32 cmxgcr; /* CMX general clock route register */
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u32 cmxsi1cr_l; /* CMX SI1 clock route low register */
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@ -102,8 +110,7 @@ typedef struct qe_mux {
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u8 res0[0x1C];
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} __attribute__ ((packed)) qe_mux_t;
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/* QE Timers
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*/
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/* QE Timers */
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typedef struct qe_timers {
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u8 gtcfr1; /* Timer 1 2 global configuration register */
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u8 res0[0x3];
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@ -133,8 +140,7 @@ typedef struct qe_timers {
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u8 res2[0x46];
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} __attribute__ ((packed)) qe_timers_t;
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/* BRG
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*/
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/* BRG */
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typedef struct qe_brg {
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u32 brgc1; /* BRG1 configuration register */
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u32 brgc2; /* BRG2 configuration register */
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@ -155,8 +161,7 @@ typedef struct qe_brg {
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u8 res0[0x40];
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} __attribute__ ((packed)) qe_brg_t;
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/* SPI
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*/
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/* SPI */
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typedef struct spi {
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u8 res0[0x20];
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u32 spmode; /* SPI mode register */
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@ -174,8 +179,7 @@ typedef struct spi {
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u8 res7[0x8];
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} __attribute__ ((packed)) spi_t;
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/* SI
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*/
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/* SI */
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typedef struct si1 {
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u16 siamr1; /* SI1 TDMA mode register */
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u16 sibmr1; /* SI1 TDMB mode register */
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@ -222,16 +226,14 @@ typedef struct si1 {
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u8 res9[0xBB];
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} __attribute__ ((packed)) si1_t;
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/* SI Routing Tables
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*/
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/* SI Routing Tables */
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typedef struct sir {
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u8 tx[0x400];
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u8 rx[0x400];
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u8 res0[0x800];
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} __attribute__ ((packed)) sir_t;
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/* USB Controller.
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*/
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/* USB Controller. */
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typedef struct usb_ctlr {
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u8 usb_usmod;
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u8 usb_usadr;
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@ -253,8 +255,7 @@ typedef struct usb_ctlr {
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u8 res6[0x22];
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} __attribute__ ((packed)) usb_t;
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/* MCC
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*/
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/* MCC */
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typedef struct mcc {
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u32 mcce; /* MCC event register */
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u32 mccm; /* MCC mask register */
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@ -263,8 +264,7 @@ typedef struct mcc {
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u8 res0[0xF0];
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} __attribute__ ((packed)) mcc_t;
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/* QE UCC Slow
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*/
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/* QE UCC Slow */
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typedef struct ucc_slow {
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u32 gumr_l; /* UCCx general mode register (low) */
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u32 gumr_h; /* UCCx general mode register (high) */
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@ -368,8 +368,7 @@ typedef struct ucc_ethernet {
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u8 res5[0x200 - 0x1c4];
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} __attribute__ ((packed)) uec_t;
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/* QE UCC Fast
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*/
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/* QE UCC Fast */
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typedef struct ucc_fast {
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u32 gumr; /* UCCx general mode register */
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u32 upsmr; /* UCCx protocol-specific mode register */
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@ -403,8 +402,7 @@ typedef struct ucc_fast {
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uec_t ucc_eth;
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} __attribute__ ((packed)) ucc_fast_t;
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/* QE UCC
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*/
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/* QE UCC */
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typedef struct ucc_common {
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u8 res1[0x90];
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u8 guemr;
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@ -419,8 +417,7 @@ typedef struct ucc {
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};
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} __attribute__ ((packed)) ucc_t;
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/* MultiPHY UTOPIA POS Controllers (UPC)
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*/
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/* MultiPHY UTOPIA POS Controllers (UPC) */
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typedef struct upc {
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u32 upgcr; /* UTOPIA/POS general configuration register */
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u32 uplpa; /* UTOPIA/POS last PHY address */
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@ -476,8 +473,7 @@ typedef struct upc {
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u8 res2[0x150];
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} __attribute__ ((packed)) upc_t;
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/* SDMA
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*/
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/* SDMA */
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typedef struct sdma {
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u32 sdsr; /* Serial DMA status register */
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u32 sdmr; /* Serial DMA mode register */
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@ -497,8 +493,7 @@ typedef struct sdma {
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u8 res2[0x38];
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} __attribute__ ((packed)) sdma_t;
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/* Debug Space
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*/
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/* Debug Space */
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typedef struct dbg {
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u32 bpdcr; /* Breakpoint debug command register */
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u32 bpdsr; /* Breakpoint debug status register */
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@ -582,40 +577,9 @@ typedef struct qe_immap {
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u8 res14[0x300];
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u8 res15[0x3A00];
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u8 res16[0x8000]; /* 0x108000 - 0x110000 */
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#if defined(CONFIG_MPC8568)
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u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */
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u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */
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#elif defined(CONFIG_MPC8569)
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u8 muram[0x20000]; /* 0x1_0000 - 0x3_0000 Multi-user RAM */
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u8 res17[0x10000]; /* 0x3_0000 - 0x4_0000 */
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#else
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u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
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u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
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u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
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#endif
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u8 muram[QE_MURAM_SIZE];
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} __attribute__ ((packed)) qe_map_t;
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extern qe_map_t *qe_immr;
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#if defined(CONFIG_MPC8568)
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#define QE_MURAM_SIZE 0x10000UL
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#elif defined(CONFIG_MPC8569)
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#define QE_MURAM_SIZE 0x20000UL
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#elif defined(CONFIG_MPC8360)
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#define QE_MURAM_SIZE 0xc000UL
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#elif defined(CONFIG_MPC832x)
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#define QE_MURAM_SIZE 0x4000UL
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#endif
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#if defined(CONFIG_MPC8323)
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#elif defined(CONFIG_MPC8569)
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#define MAX_QE_RISC 4
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#define QE_NUM_OF_SNUM 46
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#else
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#define MAX_QE_RISC 2
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#define QE_NUM_OF_SNUM 28
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#endif
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#endif /* __IMMAP_QE_H__ */
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