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arm: Move FSL_HAS_DP_DDR and NUM_DDR_CONTROLLERS to Kconfig
Move this option to Kconfig and clean up existing uses. NUM_DDR_CONTROLLERS is also used by PowerPC SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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@ -50,6 +50,11 @@ config MAX_CPUS
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cores, count the reserved ports. This will allocate enough memory
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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in spin table to properly handle all cores.
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config NUM_DDR_CONTROLLERS
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int "Maximum DDR controllers"
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default 3 if ARCH_LS2080A
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default 1
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config SYS_FSL_IFC_BANK_COUNT
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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int "Maximum banks of Integrated flash controller"
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depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
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depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
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@ -57,4 +62,7 @@ config SYS_FSL_IFC_BANK_COUNT
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default 4 if ARCH_LS1046A
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default 4 if ARCH_LS1046A
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default 8 if ARCH_LS2080A
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default 8 if ARCH_LS2080A
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config SYS_FSL_HAS_DP_DDR
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bool
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endmenu
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endmenu
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@ -30,8 +30,6 @@
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#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
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#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
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#ifdef CONFIG_LS2080A
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#ifdef CONFIG_LS2080A
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#define CONFIG_NUM_DDR_CONTROLLERS 3
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#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
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#define SRDS_MAX_LANES 8
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#define SRDS_MAX_LANES 8
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#define CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_FSL_SRDS_1
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@ -150,7 +148,6 @@
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#elif defined(CONFIG_FSL_LSCH2)
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#elif defined(CONFIG_FSL_LSCH2)
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_FSL_SEC_COMPAT 5
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#define CONFIG_SYS_FSL_SEC_COMPAT 5
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
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#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
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#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
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