board/BuR/brppt1: convert brppt1 boards to driver model

- add a devicetree for each variant (mmc, spi, nand)
- drop unneeded code from board and bur/common
- drop unneeded stuff from config header files
- minor adaptions to be compliant with driver model (requesting gpio,..)
- harmonize the commandset over all brppt1 targets

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
This commit is contained in:
Hannes Schmelzer 2018-07-06 15:41:28 +02:00 committed by Tom Rini
parent 19aa4ac09d
commit fbc7c7decf
10 changed files with 1248 additions and 154 deletions

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 B&R Industrial Automation GmbH
* http://www.br-automation.com
*
*/
/dts-v1/;
#include "am33xx.dtsi"
/ {
model = "BRPPT1 (MMC) Panel";
compatible = "ti,am33xx";
fset: factory-settings {
bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
version = <0x0100>;
order-no = "6PPT30 (MMC)";
hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
serial-no = "0";
device-id = <0x0>;
parent-id = <0x0>;
hw-variant = <0x1>;
};
aliases {
ds1bkl0 = &pwmbacklight;
ds1bkl1 = &tps_bl;
ds1timing = &timing0;
ds1ctrl = &lcdc;
gpmc = &gpmc;
mmc = &mmc2;
fset = &fset;
};
chosen {
bootargs = "console=ttyO0,115200 earlyprintk";
stdout-path = &uart0;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
panel {
status = "disabled";
compatible = "ti,tilcdc,panel";
enable-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
backlight = <&pwmbacklight>;
bkl-pwm = <&pwmbacklight>;
bkl-tps = <&tps_bl>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
native-mode = <&timing0>;
timing0: lcd {
clock-frequency = <32000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <2>;
hback-porch = <192>;
hsync-len = <1>;
vfront-porch = <20>;
vback-porch = <2>;
vsync-len = <1>;
hsync-active = <1>;
vsync-active = <1>;
pupdelay = <10>;
pondelay = <10>;
};
};
};
vmmcsd_fixed: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
pwm0: omap-pwm@timer5 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer5>;
#pwm-cells = <3>;
};
pwm1: omap-pwm@timer6 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer6>;
#pwm-cells = <3>;
};
beeper: pwm-beep {
compatible = "pwm-beeper";
pwms = <&pwm0 0 0 0>;
};
pwmbacklight: pwm-bkl {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000 0>;
default-brightness-level = <255>;
brightness-levels = <0 16 32 64 128 170 202 234 255>;
power-supply = <&vmmcsd_fixed>;
enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};
};
&uart0 { /* console uart */
u-boot,dm-spl;
status = "okay";
};
&uart1 {
status = "okay";
};
&i2c0 {
u-boot,dm-spl;
status = "okay";
clock-frequency = <400000>;
tps: tps@24 { /* PMIC controller */
u-boot,dm-spl;
reg = <0x24>;
compatible = "ti,tps65217";
tps_bl: backlight {
compatible = "ti,tps65217-bl";
isel = <1>; /* 1 - ISET1, 2 ISET2 */
fdim = <1000>; /* TPS65217_BL_FDIM_1kHZ */
default-brightness = <50>;
};
};
};
&i2c2 {
status = "okay";
clock-frequency = <100000>;
};
&edma {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&davinci_mdio {
status = "okay";
phy0: ethernet-phy@0 {
reg = <1>;
};
phy1: ethernet-phy@1 {
reg = <2>;
};
};
&mac {
status = "okay";
};
&cpsw_emac0 {
phy-handle = <&phy0>;
dual_emac_res_vlan = <1>;
phy-mode = "mii";
};
&cpsw_emac1 {
phy-handle = <&phy1>;
dual_emac_res_vlan = <2>;
phy-mode = "mii";
};
&mmc1 {
u-boot,dm-spl;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x4>;
ti,non-removable;
ti,needs-special-hs-handling;
ti,vcc-aux-disable-is-sleep;
status = "okay";
};
&mmc2 {
u-boot,dm-spl;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x8>;
ti,non-removable;
ti,needs-special-hs-handling;
ti,vcc-aux-disable-is-sleep;
status = "okay";
};
&lcdc {
status = "disabled";
};
&elm {
status = "okay";
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};
&gpio0 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio1 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio2 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio3 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&wdt2 {
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&tscadc {
status = "okay";
tsc {
ti,wires = <4>;
ti,x-plate-resistance = <200>;
ti,zx-cutoff-ratio = <40>;
ti,min_deviation = <60>;
ti,max_deviation = <600>;
ti,coordinate-readouts = <5>;
ti,wire-config = <0x00 0x11 0x22 0x33>;
bnr-buttons {
Home-Button {};
};
};
adc {
ti,adc-channels = <5 6 7>;
};
};
&timer6 { /* used for cpsw end device */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer7 { /* used for cpsw end device */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&wdt2 {
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&epwmss0 {
status = "okay";
};
&tscadc {
status = "okay";
};
&dcan0 {
status = "okay";
};
&dcan1 {
status = "okay";
};
&sham {
status = "disabled";
};
&aes {
status = "disabled";
};
&rng {
status = "disabled";
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 B&R Industrial Automation GmbH
* http://www.br-automation.com
*
*/
/dts-v1/;
#include "am33xx.dtsi"
/ {
model = "BRPPT1 (NAND) Panel";
compatible = "ti,am33xx";
fset: factory-settings {
bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
version = <0x0100>;
order-no = "6PPT30 (NAND)";
hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
serial-no = "0";
device-id = <0x0>;
parent-id = <0x0>;
hw-variant = <0x1>;
};
aliases {
ds1bkl0 = &pwmbacklight;
ds1bkl1 = &tps_bl;
ds1timing = &timing0;
ds1ctrl = &lcdc;
gpmc = &gpmc;
mmc = &mmc2;
fset = &fset;
};
chosen {
bootargs = "console=ttyO0,115200 earlyprintk";
stdout-path = &uart0;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
panel {
status = "disabled";
compatible = "ti,tilcdc,panel";
enable-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
backlight = <&pwmbacklight>;
bkl-pwm = <&pwmbacklight>;
bkl-tps = <&tps_bl>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
native-mode = <&timing0>;
timing0: lcd {
clock-frequency = <32000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <2>;
hback-porch = <192>;
hsync-len = <1>;
vfront-porch = <20>;
vback-porch = <2>;
vsync-len = <1>;
hsync-active = <1>;
vsync-active = <1>;
pupdelay = <10>;
pondelay = <10>;
};
};
};
vmmcsd_fixed: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
pwm0: omap-pwm@timer5 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer5>;
#pwm-cells = <3>;
};
pwm1: omap-pwm@timer6 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer6>;
#pwm-cells = <3>;
};
beeper: pwm-beep {
compatible = "pwm-beeper";
pwms = <&pwm0 0 0 0>;
};
pwmbacklight: pwm-bkl {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000 0>;
default-brightness-level = <255>;
brightness-levels = <0 16 32 64 128 170 202 234 255>;
power-supply = <&vmmcsd_fixed>;
enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};
};
&uart0 { /* console uart */
u-boot,dm-spl;
status = "okay";
};
&uart1 {
status = "okay";
};
&i2c0 {
u-boot,dm-spl;
status = "okay";
clock-frequency = <400000>;
tps: tps@24 { /* PMIC controller */
u-boot,dm-spl;
reg = <0x24>;
compatible = "ti,tps65217";
tps_bl: backlight {
compatible = "ti,tps65217-bl";
isel = <1>; /* 1 - ISET1, 2 ISET2 */
fdim = <1000>; /* TPS65217_BL_FDIM_1kHZ */
default-brightness = <50>;
};
};
};
&i2c2 {
status = "okay";
clock-frequency = <100000>;
};
&edma {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&davinci_mdio {
status = "okay";
phy0: ethernet-phy@0 {
reg = <1>;
};
phy1: ethernet-phy@1 {
reg = <2>;
};
};
&mac {
dual_emac;
status = "okay";
};
&cpsw_emac0 {
phy-handle = <&phy0>;
dual_emac_res_vlan = <1>;
phy-mode = "mii";
};
&cpsw_emac1 {
phy-handle = <&phy1>;
dual_emac_res_vlan = <2>;
phy-mode = "mii";
};
&mmc2 {
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x4>;
ti,non-removable;
ti,needs-special-hs-handling;
ti,vcc-aux-disable-is-sleep;
status = "disabled";
};
&lcdc {
status = "disabled";
};
&elm {
status = "okay";
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};
&gpio0 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio1 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio2 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio3 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&wdt2 {
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&tscadc {
status = "okay";
tsc {
ti,wires = <4>;
ti,x-plate-resistance = <200>;
ti,zx-cutoff-ratio = <40>;
ti,min_deviation = <60>;
ti,max_deviation = <600>;
ti,coordinate-readouts = <5>;
ti,wire-config = <0x00 0x11 0x22 0x33>;
bnr-buttons {
Home-Button {};
};
};
adc {
ti,adc-channels = <5 6 7>;
};
};
&gpmc {
u-boot,dm-spl;
status = "okay";
pinctrl-names = "default";
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
rb-gpios = <&gpmc 1 GPIO_ACTIVE_HIGH>; /* gpmc_wait1 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
gpmc,wait-pin = <1>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.MLO";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.cfgscr";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.dtb";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.u-boot-env";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot";
reg = <0x00080000 0x00080000>;
};
partition@5 {
label = "NAND.kernel";
reg = <0x00100000 0x00400000>;
};
partition@6 {
label = "NAND.rootfs";
reg = <0x00500000 0x08000000>;
};
partition@7 {
label = "NAND.user";
reg = <0x08500000 0x17b00000>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 B&R Industrial Automation GmbH
* http://www.br-automation.com
*
*/
/dts-v1/;
#include "am33xx.dtsi"
/ {
model = "BRPPT1 (MMC) Panel";
compatible = "ti,am33xx";
fset: factory-settings {
bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
version = <0x0100>;
order-no = "6PPT30 (SPI)";
hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
serial-no = "0";
device-id = <0x0>;
parent-id = <0x0>;
hw-variant = <0x1>;
};
aliases {
ds1bkl0 = &pwmbacklight;
ds1bkl1 = &tps_bl;
ds1timing = &timing0;
ds1ctrl = &lcdc;
gpmc = &gpmc;
mmc = &mmc2;
spi0 = &spi0;
fset = &fset;
};
chosen {
bootargs = "console=ttyO0,115200 earlyprintk";
stdout-path = &uart0;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
panel {
status = "disabled";
compatible = "ti,tilcdc,panel";
enable-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
backlight = <&pwmbacklight>;
bkl-pwm = <&pwmbacklight>;
bkl-tps = <&tps_bl>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
native-mode = <&timing0>;
timing0: lcd {
clock-frequency = <32000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <2>;
hback-porch = <192>;
hsync-len = <1>;
vfront-porch = <20>;
vback-porch = <2>;
vsync-len = <1>;
hsync-active = <1>;
vsync-active = <1>;
pupdelay = <10>;
pondelay = <10>;
};
};
};
vmmcsd_fixed: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
pwm0: omap-pwm@timer5 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer5>;
#pwm-cells = <3>;
};
pwm1: omap-pwm@timer6 {
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer6>;
#pwm-cells = <3>;
};
beeper: pwm-beep {
compatible = "pwm-beeper";
pwms = <&pwm0 0 0 0>;
};
pwmbacklight: pwm-bkl {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000 0>;
default-brightness-level = <255>;
brightness-levels = <0 16 32 64 128 170 202 234 255>;
power-supply = <&vmmcsd_fixed>;
enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};
};
&uart0 { /* console uart */
u-boot,dm-spl;
status = "okay";
};
&uart1 {
status = "okay";
};
&i2c0 {
u-boot,dm-spl;
status = "okay";
clock-frequency = <400000>;
tps: tps@24 { /* PMIC controller */
u-boot,dm-spl;
reg = <0x24>;
compatible = "ti,tps65217";
tps_bl: backlight {
compatible = "ti,tps65217-bl";
isel = <1>; /* 1 - ISET1, 2 ISET2 */
fdim = <1000>; /* TPS65217_BL_FDIM_1kHZ */
default-brightness = <50>;
};
};
};
&i2c2 {
status = "okay";
clock-frequency = <100000>;
};
&spi0 {
u-boot,dm-spl;
status = "okay";
cs-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>,
<&gpio0 6 GPIO_ACTIVE_HIGH>,
<0>,
<0>;
spi-max-frequency = <24000000>;
spi_flash: spiflash@0 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
compatible = "spidev", "spi-flash";
spi-max-frequency = <24000000>;
reg = <0>;
};
};
&edma {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&davinci_mdio {
status = "okay";
phy0: ethernet-phy@0 {
reg = <1>;
};
phy1: ethernet-phy@1 {
reg = <2>;
};
};
&mac {
status = "okay";
};
&cpsw_emac0 {
phy-handle = <&phy0>;
dual_emac_res_vlan = <1>;
phy-mode = "mii";
};
&cpsw_emac1 {
phy-handle = <&phy1>;
dual_emac_res_vlan = <2>;
phy-mode = "mii";
};
&mmc1 {
u-boot,dm-spl;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x4>;
ti,non-removable;
ti,needs-special-hs-handling;
ti,vcc-aux-disable-is-sleep;
status = "okay";
};
&mmc2 {
u-boot,dm-spl;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x8>;
ti,non-removable;
ti,needs-special-hs-handling;
ti,vcc-aux-disable-is-sleep;
status = "okay";
};
&lcdc {
status = "disabled";
};
&elm {
status = "okay";
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};
&gpio0 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio1 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio2 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio3 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&wdt2 {
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&tscadc {
status = "okay";
tsc {
ti,wires = <4>;
ti,x-plate-resistance = <200>;
ti,zx-cutoff-ratio = <40>;
ti,min_deviation = <60>;
ti,max_deviation = <600>;
ti,coordinate-readouts = <5>;
ti,wire-config = <0x00 0x11 0x22 0x33>;
bnr-buttons {
Home-Button {};
};
};
adc {
ti,adc-channels = <5 6 7>;
};
};
&timer6 { /* used for cpsw end device */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer7 { /* used for cpsw end device */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&wdt2 {
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&epwmss0 {
status = "okay";
};
&tscadc {
status = "okay";
};
&dcan0 {
status = "okay";
};
&dcan1 {
status = "okay";
};
&sham {
status = "disabled";
};
&aes {
status = "disabled";
};
&rng {
status = "disabled";
};

View File

@ -77,6 +77,8 @@ static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
int rc;
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
/*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
@ -108,8 +110,21 @@ void am33xx_spl_board_init(void)
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
pmicsetup(0);
gpio_direction_output(64+29, 1); /* switch NAND_RnB to GPMC_WAIT1 */
gpio_direction_output(64+28, 1); /* switch MII2_CRS to GPMC_WAIT0 */
/* peripheral reset */
rc = gpio_request(64 + 29, "GPMC_WAIT1");
if (rc != 0)
printf("cannot request GPMC_WAIT1 GPIO!\n");
rc = gpio_direction_output(64 + 29, 1);
if (rc != 0)
printf("cannot set GPMC_WAIT1 GPIO!\n");
rc = gpio_request(64 + 28, "GPMC_WAIT0");
if (rc != 0)
printf("cannot request GPMC_WAIT0 GPIO!\n");
rc = gpio_direction_output(64 + 28, 1);
if (rc != 0)
printf("cannot set GPMC_WAIT0 GPIO!\n");
}
const struct dpll_params *get_dpll_ddr_params(void)
@ -151,10 +166,13 @@ int board_late_init(void)
{
unsigned char bmode = 0;
ulong bootcount = 0;
int rc;
bootcount = bootcount_load() & 0xF;
if (gpio_get_value(REPSWITCH) == 0 || bootcount == 12)
rc = gpio_request(REPSWITCH, "REPSWITCH");
if (rc != 0 || gpio_get_value(REPSWITCH) == 0 || bootcount == 12)
bmode = 12;
else if (bootcount > 0)
bmode = 0;

View File

@ -22,15 +22,11 @@
#include <asm/io.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
#include <lcd.h>
#include "bur_common.h"
#include "../../../drivers/video/am335x-fb.h"
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
DECLARE_GLOBAL_DATA_PTR;
/* --------------------------------------------------------------------------*/
@ -270,6 +266,9 @@ int ft_board_setup(void *blob, bd_t *bd)
}
#ifdef CONFIG_SPL_BUILD
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
void pmicsetup(u32 mpupll)
{
int mpu_vdd;
@ -354,100 +353,6 @@ void set_mux_conf_regs(void)
#endif /* CONFIG_SPL_BUILD */
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
/* describing port offsets of TI's CPSW block */
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 1,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 2,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
#endif /* CONFIG_DRIVER_TI_CPSW, ... */
#if defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
int board_eth_init(bd_t *bis)
{
int rv = 0;
char mac_addr[6];
const char *mac = 0;
uint32_t mac_hi, mac_lo;
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (!env_get("ethaddr")) {
if (!mac) {
printf("<ethaddr> not set. validating E-fuse MAC ... ");
if (is_valid_ethaddr((const u8 *)mac_addr))
mac = (const char *)mac_addr;
}
if (mac) {
printf("using: %pM on ", mac);
eth_env_set_enetaddr("ethaddr", (const u8 *)mac);
}
}
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
rv = cpsw_register(&cpsw_data);
if (rv < 0) {
printf("Error %d registering CPSW switch\n", rv);
return 0;
}
return rv;
}
#endif /* defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) */
#if defined(CONFIG_MMC)
int board_mmc_init(bd_t *bis)
{
int rc = 0;
rc |= omap_mmc_init(0, 0, 0, -1, -1);
rc |= omap_mmc_init(1, 0, 0, -1, -1);
return rc;
}
#endif
int overwrite_console(void)
{
return 1;

View File

@ -3,13 +3,18 @@ CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_AM33XX=y
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-mmc"
CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
@ -20,8 +25,9 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
@ -34,29 +40,56 @@ CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_BKOPS_ENABLE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupt-controller interrupt-cells dma-names dmas "
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NETCONSOLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_OF_TRANSLATE is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_NATSEMI=y
CONFIG_DM_ETH=y
CONFIG_DRIVER_TI_CPSW=y
# CONFIG_NETDEVICES is not set
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_LZO=y
# CONFIG_OF_LIBFDT_OVERLAY is not set
# CONFIG_EFI_LOADER is not set

View File

@ -3,12 +3,16 @@ CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM33XX=y
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-nand"
CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run b_default"
@ -19,6 +23,9 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@ -32,15 +39,17 @@ CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@ -49,16 +58,42 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(MLO),128k(cfgscr),128k(dtb),128k(u-boot-env),512k(u-boot),4m(kernel),128m(rootfs),-(user)"
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupt-controller interrupt-cells dma-names dmas "
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NETCONSOLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_OF_TRANSLATE is not set
CONFIG_BLK=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_PHY_NATSEMI=y
CONFIG_DM_ETH=y
CONFIG_DRIVER_TI_CPSW=y
# CONFIG_NETDEVICES is not set
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_LZO=y
# CONFIG_OF_LIBFDT_OVERLAY is not set
# CONFIG_EFI_LOADER is not set

View File

@ -3,15 +3,18 @@ CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_AM33XX=y
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-spi"
CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
# CONFIG_EXPERT is not set
# CONFIG_FIT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=0
CONFIG_USE_BOOTCOMMAND=y
@ -23,6 +26,9 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER_SUPPORT=y
@ -38,37 +44,65 @@ CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_BKOPS_ENABLE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_MTDPARTS=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupt-controller interrupt-cells dma-names dmas "
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NETCONSOLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_OF_TRANSLATE is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHY_NATSEMI=y
CONFIG_DM_ETH=y
CONFIG_DRIVER_TI_CPSW=y
# CONFIG_NETDEVICES is not set
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_LZO=y
# CONFIG_OF_LIBFDT_OVERLAY is not set
# CONFIG_EFI_LOADER is not set

View File

@ -37,13 +37,13 @@
#endif /* CONFIG_EMMC_BOOT */
/*
* When we have SPI or NAND flash we expect to be making use of mtdparts,
* When we have NAND flash we expect to be making use of mtdparts,
* both for ease of use in U-Boot and for passing information on to
* the Linux kernel.
*/
#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND)
#if defined(CONFIG_NAND)
#define CONFIG_MTD_DEVICE /* Required for mtdparts */
#endif /* CONFIG_SPI_BOOT, ... */
#endif
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_BASE
@ -95,7 +95,7 @@
"b_tgts_pme=net usb0 mmc0 mmc1\0" \
"loaddev=mmc 1\0"
#ifdef CONFIG_MMC
#ifdef CONFIG_ENV_IS_IN_MMC
#define MMCTGTS \
MMCSPI_TGTS \
"cfgscr=mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr}\0"
@ -167,37 +167,32 @@ NANDTGTS \
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_NAND_OMAP_GPMC_WSCFG 1
#endif /* CONFIG_NAND */
/* USB configuration */
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
#if defined(CONFIG_SPI_BOOT)
/* McSPI IP block */
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#if defined(CONFIG_SPI)
/* SPI Flash */
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
/* Environment */
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
#elif defined(CONFIG_EMMC_BOOT)
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
#define CONFIG_ENV_OFFSET 0x20000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_SECT_SIZE)
#elif defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#elif defined(CONFIG_NAND)
#elif defined(CONFIG_ENV_IS_IN_NAND)
/* No NAND env support in SPL */
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE

View File

@ -11,6 +11,19 @@
#ifndef __BUR_AM335X_COMMON_H__
#define __BUR_AM335X_COMMON_H__
/* ------------------------------------------------------------------------- */
/* legacy #defines for non DM bur-board */
#ifndef CONFIG_DM
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
#define CONFIG_SYS_NS16550_COM1 0x44e09000
#define CONFIG_I2C
#define CONFIG_SYS_I2C
#endif /* CONFIG_DM */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Timer information */
@ -20,16 +33,6 @@
#include <asm/arch/omap.h>
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
/* Network defines */
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_PHY_NATSEMI
/*
* SPL related defines. The Public RAM memory map the ROM defines the
* area between 0x402F0400 and 0x4030B800 as a download area and
@ -65,9 +68,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)
/* I2C */
#define CONFIG_SYS_I2C
/*
* Our platforms make use of SPL to initalize the hardware (primarily
* memory) enough for full U-Boot to be loaded. We also support Falcon