mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 15:40:29 +09:00
-----------------------------------
- imx8: add capricorn giedi deneb boards - imx6: fixed fow wandboard - imx7: DM_ETHER for pico-imx7d - fsl_esdhc_imx: add broken-cd property - New SOC: IMXRT10xx Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/637126531 -----BEGIN PGP SIGNATURE----- iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAl4fDV8PHHNiYWJpY0Bk ZW54LmRlAAoJECjE2NMq1et3rIoMAJpEFx8ModHg3Xx69zQDcjHgzQn+dPatKgZc btSMCuAU3Toxifxj+/QR1NNNNYLBFG4BneqahbKV/c3seIbQjPJLxqTf4ceAJY6o MdsbcYSm8KwkLv2UWHV0CHTKtVJzNAxprPoW5ZxrULDORPyl56hdUWOKiDnKPx0z /vUeF7R3jglIMZ84rEDLSOew0xiYxhicMXfZB4oc2Jj8lXrpSHYf4adFitk9zG1j dumCkYSfDVyqeZytbkDa0CEZdJrXuy+tat2nTc30Asb4g/HoAuuST33cO29IMwqC foz3SMRFYgpHahYhVyNW8X+qLPxXGvIWi9md3fm9dNc44MRjVdj0dIq+vVY5lbct FWkayqmeMZLHLzzlbziIOsgDSo4n12MtAfcA8fLDN6OcxJL13A2xfR6E6BoaCgwY a7SRJWvr9AnVayOAH07rCCMvJNtppD5fi54a65LEKs7cUgeUY030ebhhqvzcDosH n++s1ukmD44yoX6vxruDQz2yWcmW3Q== =v3rf -----END PGP SIGNATURE----- Merge tag 'u-boot-imx-20200115' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx ----------------------------------- - imx8: add capricorn giedi deneb boards - imx6: fixed fow wandboard - imx7: DM_ETHER for pico-imx7d - fsl_esdhc_imx: add broken-cd property - New SOC: IMXRT10xx Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/637126531
This commit is contained in:
commit
fb537657d9
@ -807,6 +807,14 @@ config ARCH_IMX8M
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|||||||
select SUPPORT_SPL
|
select SUPPORT_SPL
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imply CMD_DM
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imply CMD_DM
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|
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config ARCH_IMXRT
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bool "NXP i.MXRT platform"
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|
select CPU_V7M
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|
select DM
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||||||
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select DM_SERIAL
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select SUPPORT_SPL
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imply CMD_DM
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||||||
|
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||||||
config ARCH_MX23
|
config ARCH_MX23
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bool "NXP i.MX23 family"
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bool "NXP i.MX23 family"
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select CPU_ARM926EJS
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select CPU_ARM926EJS
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@ -1732,6 +1740,8 @@ source "arch/arm/mach-imx/imx8/Kconfig"
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|
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source "arch/arm/mach-imx/imx8m/Kconfig"
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source "arch/arm/mach-imx/imx8m/Kconfig"
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source "arch/arm/mach-imx/imxrt/Kconfig"
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|
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source "arch/arm/mach-imx/mxs/Kconfig"
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source "arch/arm/mach-imx/mxs/Kconfig"
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|
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source "arch/arm/mach-omap2/Kconfig"
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source "arch/arm/mach-omap2/Kconfig"
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|
@ -104,11 +104,11 @@ libs-y += arch/arm/cpu/
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libs-y += arch/arm/lib/
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libs-y += arch/arm/lib/
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|
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ifeq ($(CONFIG_SPL_BUILD),y)
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ifeq ($(CONFIG_SPL_BUILD),y)
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ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8))
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ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt))
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libs-y += arch/arm/mach-imx/
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libs-y += arch/arm/mach-imx/
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endif
|
endif
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else
|
else
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ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
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ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imxrt vf610))
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libs-y += arch/arm/mach-imx/
|
libs-y += arch/arm/mach-imx/
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endif
|
endif
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endif
|
endif
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||||||
|
@ -291,6 +291,12 @@ void flush_dcache_all(void)
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void invalidate_dcache_all(void)
|
void invalidate_dcache_all(void)
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{
|
{
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}
|
}
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|
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||||||
|
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
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|
enum dcache_option option)
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|
{
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|
}
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|
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#endif
|
#endif
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||||||
|
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||||||
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
|
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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|
@ -699,7 +699,9 @@ dtb-$(CONFIG_ARCH_IMX8) += \
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imx8qm-rom7720-a1.dtb \
|
imx8qm-rom7720-a1.dtb \
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fsl-imx8qxp-ai_ml.dtb \
|
fsl-imx8qxp-ai_ml.dtb \
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fsl-imx8qxp-colibri.dtb \
|
fsl-imx8qxp-colibri.dtb \
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fsl-imx8qxp-mek.dtb
|
fsl-imx8qxp-mek.dtb \
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|
imx8-deneb.dtb \
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|
imx8-giedi.dtb
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|
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dtb-$(CONFIG_ARCH_IMX8M) += \
|
dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mm-evk.dtb \
|
imx8mm-evk.dtb \
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@ -707,6 +709,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mq-evk.dtb \
|
imx8mq-evk.dtb \
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imx8mp-evk.dtb
|
imx8mp-evk.dtb
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||||||
|
|
||||||
|
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
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|
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dtb-$(CONFIG_RCAR_GEN2) += \
|
dtb-$(CONFIG_RCAR_GEN2) += \
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r8a7790-lager-u-boot.dtb \
|
r8a7790-lager-u-boot.dtb \
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r8a7790-stout-u-boot.dtb \
|
r8a7790-stout-u-boot.dtb \
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|
@ -268,8 +268,9 @@
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reg = <0x0 0x5a800000 0x0 0x4000>;
|
reg = <0x0 0x5a800000 0x0 0x4000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
|
interrupt-parent = <&gic>;
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||||||
clocks = <&clk IMX8QXP_I2C0_CLK>;
|
clocks = <&clk IMX8QXP_I2C0_CLK>,
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||||||
clock-names = "per";
|
<&clk IMX8QXP_I2C0_IPG_CLK>;
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|
clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
|
assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
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assigned-clock-rates = <24000000>;
|
assigned-clock-rates = <24000000>;
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power-domains = <&pd_dma_lpi2c0>;
|
power-domains = <&pd_dma_lpi2c0>;
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@ -299,8 +300,9 @@
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|||||||
reg = <0x0 0x5a820000 0x0 0x4000>;
|
reg = <0x0 0x5a820000 0x0 0x4000>;
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||||||
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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||||||
interrupt-parent = <&gic>;
|
interrupt-parent = <&gic>;
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||||||
clocks = <&clk IMX8QXP_I2C2_CLK>;
|
clocks = <&clk IMX8QXP_I2C2_CLK>,
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||||||
clock-names = "per";
|
<&clk IMX8QXP_I2C2_IPG_CLK>;
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||||||
|
clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
|
assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
|
||||||
assigned-clock-rates = <24000000>;
|
assigned-clock-rates = <24000000>;
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||||||
power-domains = <&pd_dma_lpi2c2>;
|
power-domains = <&pd_dma_lpi2c2>;
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||||||
|
@ -268,6 +268,7 @@
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|||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
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||||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
pinctrl-0 = <&pinctrl_usdhc2>;
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||||||
no-1-8-v;
|
no-1-8-v;
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||||||
|
broken-cd;
|
||||||
keep-power-in-suspend;
|
keep-power-in-suspend;
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||||||
wakeup-source;
|
wakeup-source;
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status = "okay";
|
status = "okay";
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||||||
|
10
arch/arm/dts/imx8-deneb.dts
Normal file
10
arch/arm/dts/imx8-deneb.dts
Normal file
@ -0,0 +1,10 @@
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|||||||
|
// SPDX-License-Identifier: GPL-2.0+
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||||||
|
/*
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||||||
|
* Copyright 2019 Siemens AG
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||||||
|
*/
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||||||
|
|
||||||
|
#include "imx8qxp-capricorn.dtsi"
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||||||
|
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||||||
|
/ {
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||||||
|
model = "Siemens Deneb";
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||||||
|
};
|
10
arch/arm/dts/imx8-giedi.dts
Normal file
10
arch/arm/dts/imx8-giedi.dts
Normal file
@ -0,0 +1,10 @@
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|||||||
|
// SPDX-License-Identifier: GPL-2.0+
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||||||
|
/*
|
||||||
|
* Copyright 2019 Siemens AG
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "imx8qxp-capricorn.dtsi"
|
||||||
|
|
||||||
|
/ {
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||||||
|
model = "Siemens Giedi";
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||||||
|
};
|
133
arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi
Normal file
133
arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi
Normal file
@ -0,0 +1,133 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
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||||||
|
/*
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||||||
|
* Copyright 2019 Siemens AG
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||||||
|
*/
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||||||
|
|
||||||
|
&{/imx8qx-pm} {
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||||||
|
|
||||||
|
u-boot,dm-spl;
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||||||
|
};
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||||||
|
|
||||||
|
&mu {
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|
u-boot,dm-spl;
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|
};
|
||||||
|
|
||||||
|
&clk {
|
||||||
|
u-boot,dm-spl;
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||||||
|
};
|
||||||
|
|
||||||
|
&iomuxc {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_lsio {
|
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|
u-boot,dm-spl;
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||||||
|
};
|
||||||
|
|
||||||
|
&pd_lsio_gpio0 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_lsio_gpio1 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_lsio_gpio2 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_lsio_gpio3 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_lsio_gpio4 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_lsio_gpio5 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_lsio_gpio6 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_lsio_gpio7 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_dma {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_dma_lpuart0 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_dma_lpuart2 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_conn {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_conn_sdch0 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_conn_sdch1 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pd_conn_sdch2 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio0 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio1 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio2 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio3 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio4 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio5 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio6 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio7 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&lpuart0 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&lpuart2 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&usdhc1 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&usdhc2 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
285
arch/arm/dts/imx8qxp-capricorn.dtsi
Normal file
285
arch/arm/dts/imx8qxp-capricorn.dtsi
Normal file
@ -0,0 +1,285 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright 2017 NXP
|
||||||
|
*
|
||||||
|
* Copyright 2019 Siemens AG
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "fsl-imx8qxp.dtsi"
|
||||||
|
#include "imx8qxp-capricorn-u-boot.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Siemens Giedi";
|
||||||
|
compatible = "siemens,capricorn", "fsl,imx8qxp";
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
|
||||||
|
stdout-path = &lpuart2;
|
||||||
|
};
|
||||||
|
|
||||||
|
leds {
|
||||||
|
compatible = "gpio-leds";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pinctrl_gpio_leds>;
|
||||||
|
|
||||||
|
run {
|
||||||
|
label = "run";
|
||||||
|
gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
flt {
|
||||||
|
label = "flt";
|
||||||
|
gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
svc {
|
||||||
|
label = "svc";
|
||||||
|
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
com1_tx {
|
||||||
|
label = "com1-tx";
|
||||||
|
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
com1_rx {
|
||||||
|
label = "com1-rx";
|
||||||
|
gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
com2_tx {
|
||||||
|
label = "com2-tx";
|
||||||
|
gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
com2_rx {
|
||||||
|
label = "com2-rx";
|
||||||
|
gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
cloud {
|
||||||
|
label = "cloud";
|
||||||
|
gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
wlan {
|
||||||
|
label = "wlan";
|
||||||
|
gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
dbg1 {
|
||||||
|
label = "dbg1";
|
||||||
|
gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
dbg2 {
|
||||||
|
label = "dbg2";
|
||||||
|
gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
dbg3 {
|
||||||
|
label = "dbg3";
|
||||||
|
gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
dbg4 {
|
||||||
|
label = "dbg4";
|
||||||
|
gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&iomuxc {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
|
||||||
|
muxcgrp: imx8qxp-som {
|
||||||
|
pinctrl_gpio_leds: gpioledsgrp {
|
||||||
|
fsl,pins = <
|
||||||
|
SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021
|
||||||
|
SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021
|
||||||
|
SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021
|
||||||
|
SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021
|
||||||
|
SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021
|
||||||
|
SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021
|
||||||
|
SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021
|
||||||
|
SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021
|
||||||
|
SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021
|
||||||
|
SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021
|
||||||
|
SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021
|
||||||
|
SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021
|
||||||
|
SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl_lpi2c0: lpi2c0grp {
|
||||||
|
fsl,pins = <
|
||||||
|
SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x0C000020
|
||||||
|
SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x0C000020
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl_lpi2c1: lpi2c1grp {
|
||||||
|
fsl,pins = <
|
||||||
|
SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x0C000020
|
||||||
|
SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x0C000020
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl_lpuart2: lpuart2grp {
|
||||||
|
fsl,pins = <
|
||||||
|
SC_P_UART2_RX_ADMA_UART2_RX 0x06000020
|
||||||
|
SC_P_UART2_TX_ADMA_UART2_TX 0x06000020
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl_usdhc1: usdhc1grp {
|
||||||
|
fsl,pins = <
|
||||||
|
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
|
||||||
|
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
|
||||||
|
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
|
||||||
|
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
|
||||||
|
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
|
||||||
|
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
|
||||||
|
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
|
||||||
|
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
|
||||||
|
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
|
||||||
|
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
|
||||||
|
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
|
||||||
|
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
|
||||||
|
SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x06000021
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl_usdhc2: usdhc2grp {
|
||||||
|
fsl,pins = <
|
||||||
|
SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
|
||||||
|
SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
|
||||||
|
SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
|
||||||
|
SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
|
||||||
|
SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
|
||||||
|
SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
|
||||||
|
SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B 0x06000021
|
||||||
|
//SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021
|
||||||
|
SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x06000021
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl_fec2: fec2grp {
|
||||||
|
fsl,pins = <
|
||||||
|
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
|
||||||
|
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
|
||||||
|
SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
|
||||||
|
|
||||||
|
SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060
|
||||||
|
SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060
|
||||||
|
|
||||||
|
SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060
|
||||||
|
SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
|
||||||
|
SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
|
||||||
|
SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060
|
||||||
|
SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
|
||||||
|
SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
|
||||||
|
SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
|
||||||
|
SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 /* ERST: Reset pin */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c0 {
|
||||||
|
clock-frequency = <100000>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pinctrl_lpi2c0>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c1 {
|
||||||
|
clock-frequency = <100000>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pinctrl_lpi2c1>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&lpuart2 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pinctrl_lpuart2>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usdhc1 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||||
|
clock-frequency=<52000000>;
|
||||||
|
no-1-8-v;
|
||||||
|
bus-width = <8>;
|
||||||
|
non-removable;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio1 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio2 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio3 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio4 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio5 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&fec1 {
|
||||||
|
status ="disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&fec2 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pinctrl_fec2>;
|
||||||
|
phy-mode = "rmii";
|
||||||
|
|
||||||
|
phy-handle = <ðphy1>;
|
||||||
|
fsl,magic-packet;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
mdio {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
ethphy0: ethernet-phy@0 {
|
||||||
|
compatible = "ethernet-phy-ieee802.3-c22";
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
ethphy1: ethernet-phy@1 {
|
||||||
|
compatible = "ethernet-phy-ieee802.3-c22";
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
44
arch/arm/dts/imxrt1050-evk-u-boot.dtsi
Normal file
44
arch/arm/dts/imxrt1050-evk-u-boot.dtsi
Normal file
@ -0,0 +1,44 @@
|
|||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/ {
|
||||||
|
chosen {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&lpuart1 { /* console */
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&semc {
|
||||||
|
bank1: bank@0 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&iomuxc {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
|
||||||
|
imxrt1050-evk {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
pinctrl_lpuart1: lpuart1grp {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl_semc: semcgrp {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl_usdhc0: usdhc0grp {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&usdhc1 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
200
arch/arm/dts/imxrt1050-evk.dts
Normal file
200
arch/arm/dts/imxrt1050-evk.dts
Normal file
@ -0,0 +1,200 @@
|
|||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include "imxrt1050.dtsi"
|
||||||
|
#include "imxrt1050-evk-u-boot.dtsi"
|
||||||
|
#include <dt-bindings/pinctrl/pins-imxrt1050.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "NXP IMXRT1050-evk board";
|
||||||
|
compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
bootargs = "root=/dev/ram";
|
||||||
|
stdout-path = "serial0:115200n8";
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
reg = <0x80000000 0x2000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&lpuart1 { /* console */
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pinctrl_lpuart1>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&semc {
|
||||||
|
/*
|
||||||
|
* Memory configuration from sdram datasheet IS42S16160J-6BLI
|
||||||
|
*/
|
||||||
|
fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
|
||||||
|
MUX_CSX0_SDRAM_CS1
|
||||||
|
0
|
||||||
|
0
|
||||||
|
0
|
||||||
|
0>;
|
||||||
|
fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
|
||||||
|
BL_8
|
||||||
|
COL_9BITS
|
||||||
|
CL_3>;
|
||||||
|
fsl,sdram-timing = /bits/ 8 <0x2
|
||||||
|
0x2
|
||||||
|
0x9
|
||||||
|
0x1
|
||||||
|
0x5
|
||||||
|
0x6
|
||||||
|
|
||||||
|
0x20
|
||||||
|
0x09
|
||||||
|
0x01
|
||||||
|
0x00
|
||||||
|
|
||||||
|
0x04
|
||||||
|
0x0A
|
||||||
|
0x21
|
||||||
|
0x50>;
|
||||||
|
|
||||||
|
bank1: bank@0 {
|
||||||
|
fsl,base-address = <0x80000000>;
|
||||||
|
fsl,memory-size = <MEM_SIZE_32M>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&iomuxc {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pinctrl_lpuart1>;
|
||||||
|
|
||||||
|
imxrt1050-evk {
|
||||||
|
pinctrl_lpuart1: lpuart1grp {
|
||||||
|
fsl,pins = <
|
||||||
|
MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
|
||||||
|
0xf1
|
||||||
|
MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
|
||||||
|
0xf1
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl_semc: semcgrp {
|
||||||
|
fsl,pins = <
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
|
||||||
|
0xf1 /* SEMC_D0 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
|
||||||
|
0xf1 /* SEMC_D1 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
|
||||||
|
0xf1 /* SEMC_D2 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
|
||||||
|
0xf1 /* SEMC_D3 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
|
||||||
|
0xf1 /* SEMC_D4 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
|
||||||
|
0xf1 /* SEMC_D5 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
|
||||||
|
0xf1 /* SEMC_D6 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
|
||||||
|
0xf1 /* SEMC_D7 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
|
||||||
|
0xf1 /* SEMC_DM0 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
|
||||||
|
0xf1 /* SEMC_A0 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
|
||||||
|
0xf1 /* SEMC_A1 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
|
||||||
|
0xf1 /* SEMC_A2 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
|
||||||
|
0xf1 /* SEMC_A3 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
|
||||||
|
0xf1 /* SEMC_A4 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
|
||||||
|
0xf1 /* SEMC_A5 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
|
||||||
|
0xf1 /* SEMC_A6 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
|
||||||
|
0xf1 /* SEMC_A7 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
|
||||||
|
0xf1 /* SEMC_A8 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
|
||||||
|
0xf1 /* SEMC_A9 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
|
||||||
|
0xf1 /* SEMC_A11 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
|
||||||
|
0xf1 /* SEMC_A12 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
|
||||||
|
0xf1 /* SEMC_BA0 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
|
||||||
|
0xf1 /* SEMC_BA1 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
|
||||||
|
0xf1 /* SEMC_A10 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
|
||||||
|
0xf1 /* SEMC_CAS */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
|
||||||
|
0xf1 /* SEMC_RAS */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
|
||||||
|
0xf1 /* SEMC_CLK */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
|
||||||
|
0xf1 /* SEMC_CKE */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
|
||||||
|
0xf1 /* SEMC_WE */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
|
||||||
|
0xf1 /* SEMC_CS0 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
|
||||||
|
0xf1 /* SEMC_D8 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
|
||||||
|
0xf1 /* SEMC_D9 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
|
||||||
|
0xf1 /* SEMC_D10 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
|
||||||
|
0xf1 /* SEMC_D11 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
|
||||||
|
0xf1 /* SEMC_D12 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
|
||||||
|
0xf1 /* SEMC_D13 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
|
||||||
|
0xf1 /* SEMC_D14 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
|
||||||
|
0xf1 /* SEMC_D15 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
|
||||||
|
0xf1 /* SEMC_DM1 */
|
||||||
|
MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
|
||||||
|
(IMX_PAD_SION | 0xf1) /* SEMC_DQS */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pinctrl_usdhc0: usdhc0grp {
|
||||||
|
fsl,pins = <
|
||||||
|
MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
|
||||||
|
0x1B000
|
||||||
|
MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
|
||||||
|
0xB069
|
||||||
|
MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
|
||||||
|
0x17061
|
||||||
|
MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
|
||||||
|
0x17061
|
||||||
|
MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
|
||||||
|
0x17061
|
||||||
|
MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
|
||||||
|
0x17061
|
||||||
|
MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
|
||||||
|
0x17061
|
||||||
|
MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
|
||||||
|
0x17061
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&usdhc1 {
|
||||||
|
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
|
||||||
|
pinctrl-0 = <&pinctrl_usdhc0>;
|
||||||
|
pinctrl-1 = <&pinctrl_usdhc0>;
|
||||||
|
pinctrl-2 = <&pinctrl_usdhc0>;
|
||||||
|
pinctrl-3 = <&pinctrl_usdhc0>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
|
||||||
|
};
|
146
arch/arm/dts/imxrt1050.dtsi
Normal file
146
arch/arm/dts/imxrt1050.dtsi
Normal file
@ -0,0 +1,146 @@
|
|||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "skeleton.dtsi"
|
||||||
|
#include "armv7-m.dtsi"
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/clock/imxrt1050-clock.h>
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
#include <dt-bindings/memory/imxrt-sdram.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
aliases {
|
||||||
|
gpio0 = &gpio1;
|
||||||
|
gpio1 = &gpio2;
|
||||||
|
gpio2 = &gpio3;
|
||||||
|
gpio3 = &gpio4;
|
||||||
|
gpio4 = &gpio5;
|
||||||
|
mmc0 = &usdhc1;
|
||||||
|
serial0 = &lpuart1;
|
||||||
|
};
|
||||||
|
|
||||||
|
clocks {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
|
||||||
|
osc {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
compatible = "fsl,imx-osc", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <24000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
|
||||||
|
semc: semc@402f0000 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
compatible = "fsl,imxrt-semc";
|
||||||
|
reg = <0x402f0000 0x4000>;
|
||||||
|
clocks = <&clks IMXRT1050_CLK_SEMC>;
|
||||||
|
pinctrl-0 = <&pinctrl_semc>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
lpuart1: serial@40184000 {
|
||||||
|
compatible = "fsl,imxrt-lpuart";
|
||||||
|
reg = <0x40184000 0x4000>;
|
||||||
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&clks IMXRT1050_CLK_LPUART1>;
|
||||||
|
clock-names = "per";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
iomuxc: iomuxc@401f8000 {
|
||||||
|
compatible = "fsl,imxrt-iomuxc";
|
||||||
|
reg = <0x401f8000 0x4000>;
|
||||||
|
fsl,mux_mask = <0x7>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clks: ccm@400fc000 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
compatible = "fsl,imxrt1050-ccm";
|
||||||
|
reg = <0x400fc000 0x4000>;
|
||||||
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
usdhc1: usdhc@402c0000 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
compatible = "fsl,imxrt-usdhc";
|
||||||
|
reg = <0x402c0000 0x10000>;
|
||||||
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&clks IMXRT1050_CLK_USDHC1>;
|
||||||
|
clock-names = "per";
|
||||||
|
bus-width = <4>;
|
||||||
|
fsl,tuning-start-tap = <20>;
|
||||||
|
fsl,tuning-step= <2>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio1: gpio@401b8000 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
|
||||||
|
reg = <0x401b8000 0x4000>;
|
||||||
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio2: gpio@401bc000 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
|
||||||
|
reg = <0x401bc000 0x4000>;
|
||||||
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio3: gpio@401c0000 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
|
||||||
|
reg = <0x401c0000 0x4000>;
|
||||||
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio4: gpio@401c4000 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
|
||||||
|
reg = <0x401c4000 0x4000>;
|
||||||
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio5: gpio@400c0000 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
|
||||||
|
reg = <0x400c0000 0x4000>;
|
||||||
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
10
arch/arm/include/asm/arch-imxrt/clock.h
Normal file
10
arch/arm/include/asm/arch-imxrt/clock.h
Normal file
@ -0,0 +1,10 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM_ARCH_CLOCK_H
|
||||||
|
#define __ASM_ARCH_CLOCK_H
|
||||||
|
|
||||||
|
#endif /* __ASM_ARCH_CLOCK_H */
|
19
arch/arm/include/asm/arch-imxrt/gpio.h
Normal file
19
arch/arm/include/asm/arch-imxrt/gpio.h
Normal file
@ -0,0 +1,19 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM_ARCH_GPIO_H__
|
||||||
|
#define __ASM_ARCH_GPIO_H__
|
||||||
|
|
||||||
|
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||||
|
/* GPIO registers */
|
||||||
|
struct gpio_regs {
|
||||||
|
u32 gpio_dr; /* data */
|
||||||
|
u32 gpio_dir; /* direction */
|
||||||
|
u32 gpio_psr; /* pad satus */
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __ASM_ARCH_GPIO_H__ */
|
20
arch/arm/include/asm/arch-imxrt/imx-regs.h
Normal file
20
arch/arm/include/asm/arch-imxrt/imx-regs.h
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright(C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM_ARCH_IMX_REGS_H__
|
||||||
|
#define __ASM_ARCH_IMX_REGS_H__
|
||||||
|
|
||||||
|
#define ARCH_MXC
|
||||||
|
|
||||||
|
#define GPIO1_BASE_ADDR 0x401B8000
|
||||||
|
#define GPIO2_BASE_ADDR 0x401BC000
|
||||||
|
#define GPIO3_BASE_ADDR 0x401C0000
|
||||||
|
#define GPIO4_BASE_ADDR 0x401C4000
|
||||||
|
#define GPIO5_BASE_ADDR 0x400C0000
|
||||||
|
|
||||||
|
#define ANATOP_BASE_ADDR 0x400d8000
|
||||||
|
|
||||||
|
#endif /* __ASM_ARCH_IMX_REGS_H__ */
|
11
arch/arm/include/asm/arch-imxrt/imxrt.h
Normal file
11
arch/arm/include/asm/arch-imxrt/imxrt.h
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _ASM_ARCH_IMXRT_H
|
||||||
|
#define _ASM_ARCH_IMXRT_H
|
||||||
|
|
||||||
|
#endif /* _ASM_ARCH_IMXRT_H */
|
||||||
|
|
11
arch/arm/include/asm/arch-imxrt/sys_proto.h
Normal file
11
arch/arm/include/asm/arch-imxrt/sys_proto.h
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2017 NXP
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _ASM_ARCH_SYS_PROTO_H
|
||||||
|
#define _ASM_ARCH_SYS_PROTO_H
|
||||||
|
|
||||||
|
#include <asm/mach-imx/sys_proto.h>
|
||||||
|
|
||||||
|
#endif /* _ASM_ARCH_SYS_PROTO_H */
|
@ -27,7 +27,7 @@ endif
|
|||||||
obj-$(CONFIG_GPT_TIMER) += timer.o
|
obj-$(CONFIG_GPT_TIMER) += timer.o
|
||||||
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
|
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
|
||||||
endif
|
endif
|
||||||
ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8))
|
ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt))
|
||||||
obj-y += misc.o
|
obj-y += misc.o
|
||||||
obj-$(CONFIG_SPL_BUILD) += spl.o
|
obj-$(CONFIG_SPL_BUILD) += spl.o
|
||||||
endif
|
endif
|
||||||
@ -226,5 +226,6 @@ obj-$(CONFIG_MX7) += mx7/
|
|||||||
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
|
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
|
||||||
obj-$(CONFIG_IMX8M) += imx8m/
|
obj-$(CONFIG_IMX8M) += imx8m/
|
||||||
obj-$(CONFIG_ARCH_IMX8) += imx8/
|
obj-$(CONFIG_ARCH_IMX8) += imx8/
|
||||||
|
obj-$(CONFIG_ARCH_IMXRT) += imxrt/
|
||||||
|
|
||||||
obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
|
obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
|
||||||
|
@ -55,6 +55,16 @@ config TARGET_COLIBRI_IMX8X
|
|||||||
select BOARD_LATE_INIT
|
select BOARD_LATE_INIT
|
||||||
select IMX8QXP
|
select IMX8QXP
|
||||||
|
|
||||||
|
config TARGET_DENEB
|
||||||
|
bool "Support i.MX8QXP Capricorn Deneb board"
|
||||||
|
select BOARD_LATE_INIT
|
||||||
|
select IMX8QXP
|
||||||
|
|
||||||
|
config TARGET_GIEDI
|
||||||
|
bool "Support i.MX8QXP Capricorn Giedi board"
|
||||||
|
select BOARD_LATE_INIT
|
||||||
|
select IMX8QXP
|
||||||
|
|
||||||
config TARGET_IMX8QM_MEK
|
config TARGET_IMX8QM_MEK
|
||||||
bool "Support i.MX8QM MEK board"
|
bool "Support i.MX8QM MEK board"
|
||||||
select BOARD_LATE_INIT
|
select BOARD_LATE_INIT
|
||||||
@ -78,5 +88,6 @@ source "board/freescale/imx8qxp_mek/Kconfig"
|
|||||||
source "board/advantech/imx8qm_rom7720_a1/Kconfig"
|
source "board/advantech/imx8qm_rom7720_a1/Kconfig"
|
||||||
source "board/toradex/apalis-imx8/Kconfig"
|
source "board/toradex/apalis-imx8/Kconfig"
|
||||||
source "board/toradex/colibri-imx8x/Kconfig"
|
source "board/toradex/colibri-imx8x/Kconfig"
|
||||||
|
source "board/siemens/capricorn/Kconfig"
|
||||||
|
|
||||||
endif
|
endif
|
||||||
|
25
arch/arm/mach-imx/imxrt/Kconfig
Normal file
25
arch/arm/mach-imx/imxrt/Kconfig
Normal file
@ -0,0 +1,25 @@
|
|||||||
|
if ARCH_IMXRT
|
||||||
|
|
||||||
|
config IMXRT
|
||||||
|
bool
|
||||||
|
|
||||||
|
config IMXRT1050
|
||||||
|
bool
|
||||||
|
select IMXRT
|
||||||
|
|
||||||
|
config SYS_SOC
|
||||||
|
default "imxrt"
|
||||||
|
|
||||||
|
choice
|
||||||
|
prompt "NXP i.MXRT board select"
|
||||||
|
optional
|
||||||
|
|
||||||
|
config TARGET_IMXRT1050_EVK
|
||||||
|
bool "Support imxrt1050 EVK board"
|
||||||
|
select IMXRT1050
|
||||||
|
|
||||||
|
endchoice
|
||||||
|
|
||||||
|
source "board/freescale/imxrt1050-evk/Kconfig"
|
||||||
|
|
||||||
|
endif
|
7
arch/arm/mach-imx/imxrt/Makefile
Normal file
7
arch/arm/mach-imx/imxrt/Makefile
Normal file
@ -0,0 +1,7 @@
|
|||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
# (C) Copyright 2019
|
||||||
|
# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
#
|
||||||
|
|
||||||
|
obj-y := soc.o
|
35
arch/arm/mach-imx/imxrt/soc.c
Normal file
35
arch/arm/mach-imx/imxrt/soc.c
Normal file
@ -0,0 +1,35 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/armv7_mpu.h>
|
||||||
|
|
||||||
|
int arch_cpu_init(void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
struct mpu_region_config imxrt1050_region_config[] = {
|
||||||
|
{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
|
||||||
|
STRONG_ORDER, REGION_4GB },
|
||||||
|
{ PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW,
|
||||||
|
O_I_WB_RD_WR_ALLOC, (ffs(PHYS_SDRAM_SIZE) - 2) },
|
||||||
|
{ DMAMEM_BASE,
|
||||||
|
REGION_2, XN_DIS, PRIV_RW_USR_RW,
|
||||||
|
STRONG_ORDER, (ffs(DMAMEM_SZ_ALL) - 2) },
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configure the memory protection unit (MPU) to allow full access to
|
||||||
|
* the whole 4GB address space.
|
||||||
|
*/
|
||||||
|
disable_mpu();
|
||||||
|
for (i = 0; i < ARRAY_SIZE(imxrt1050_region_config); i++)
|
||||||
|
mpu_config(&imxrt1050_region_config[i]);
|
||||||
|
enable_mpu();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
@ -14,28 +14,24 @@ Get and Build the ARM Trusted firmware
|
|||||||
|
|
||||||
$ git clone https://source.codeaurora.org/external/imx/imx-atf
|
$ git clone https://source.codeaurora.org/external/imx/imx-atf
|
||||||
$ cd imx-atf/
|
$ cd imx-atf/
|
||||||
$ git checkout origin/imx_4.9.88_imx8qxp_beta2 -b imx_4.9.88_imx8qxp_beta2
|
$ git checkout origin/imx_4.19.35_1.1.0 -b imx_4.19.35_1.1.0
|
||||||
$ make PLAT=imx8qxp bl31
|
$ make PLAT=imx8qx bl31
|
||||||
|
|
||||||
Get scfw_tcm.bin and ahab-container.img
|
Get scfw_tcm.bin and ahab-container.img
|
||||||
==============================
|
==============================
|
||||||
|
|
||||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-0.7.bin
|
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.2.7.1.bin
|
||||||
$ chmod +x imx-sc-firmware-0.7.bin
|
$ chmod +x imx-sc-firmware-1.2.7.1.bin
|
||||||
$ ./imx-sc-firmware-0.7.bin
|
$ ./imx-sc-firmware-1.2.7.1.bin
|
||||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.6.bin
|
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-2.3.1.bin
|
||||||
$ chmod +x firmware-imx-7.6.bin
|
$ chmod +x imx-seco-2.3.1.bin
|
||||||
$ ./firmware-imx-7.6.bin
|
$ ./imx-seco-2.3.1.bin
|
||||||
|
|
||||||
Copy the following binaries to U-Boot folder:
|
Copy the following binaries to U-Boot folder:
|
||||||
|
|
||||||
$ cp imx-atf/build/imx8qxp/release/bl31.bin .
|
$ cp imx-atf/build/imx8qx/release/bl31.bin .
|
||||||
$ cp u-boot/u-boot.bin .
|
$ cp imx-seco-2.3.1/firmware/seco/mx8qx-ahab-container.img ./ahab-container.img
|
||||||
|
$ cp imx-sc-firmware-1.2.7.1/mx8qx-mek-scfw-tcm.bin .
|
||||||
Copy the following firmwares U-Boot folder :
|
|
||||||
|
|
||||||
$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
|
|
||||||
$ cp imx-sc-firmware-0.7/mx8qx-mek-scfw-tcm.bin .
|
|
||||||
|
|
||||||
Build U-Boot
|
Build U-Boot
|
||||||
============
|
============
|
||||||
|
22
board/freescale/imxrt1050-evk/Kconfig
Normal file
22
board/freescale/imxrt1050-evk/Kconfig
Normal file
@ -0,0 +1,22 @@
|
|||||||
|
if TARGET_IMXRT1050_EVK
|
||||||
|
|
||||||
|
config SYS_BOARD
|
||||||
|
string
|
||||||
|
default "imxrt1050-evk"
|
||||||
|
|
||||||
|
config SYS_VENDOR
|
||||||
|
string
|
||||||
|
default "freescale"
|
||||||
|
|
||||||
|
config SYS_SOC
|
||||||
|
string
|
||||||
|
default "imxrt1050"
|
||||||
|
|
||||||
|
config SYS_CONFIG_NAME
|
||||||
|
string
|
||||||
|
default "imxrt1050-evk"
|
||||||
|
|
||||||
|
config IMX_CONFIG
|
||||||
|
default "board/freescale/imxrt1050-evk/imximage.cfg"
|
||||||
|
|
||||||
|
endif
|
6
board/freescale/imxrt1050-evk/MAINTAINERS
Normal file
6
board/freescale/imxrt1050-evk/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
|
|||||||
|
IMXRT1050 EVALUATION KIT
|
||||||
|
M: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
S: Maintained
|
||||||
|
F: board/freescale/imxrt1050-evk
|
||||||
|
F: include/configs/imxrt1050-evk.h
|
||||||
|
F: configs/imxrt1050-evk_defconfig
|
6
board/freescale/imxrt1050-evk/Makefile
Normal file
6
board/freescale/imxrt1050-evk/Makefile
Normal file
@ -0,0 +1,6 @@
|
|||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
# Copyright (C) 2019
|
||||||
|
# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
|
||||||
|
obj-y := imxrt1050-evk.o
|
31
board/freescale/imxrt1050-evk/README
Normal file
31
board/freescale/imxrt1050-evk/README
Normal file
@ -0,0 +1,31 @@
|
|||||||
|
How to use U-Boot on NXP i.MXRT1050 EVK
|
||||||
|
-----------------------------------------------
|
||||||
|
|
||||||
|
- Build U-Boot for i.MXRT1050 EVK:
|
||||||
|
|
||||||
|
$ make mrproper
|
||||||
|
$ make imxrt1050-evk_defconfig
|
||||||
|
$ make
|
||||||
|
|
||||||
|
This will generate the SPL image called SPL and the u-boot.img.
|
||||||
|
|
||||||
|
- Flash the SPL image into the micro SD card:
|
||||||
|
|
||||||
|
sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
|
||||||
|
|
||||||
|
- Flash the u-boot.img image into the micro SD card:
|
||||||
|
|
||||||
|
sudo dd if=u-boot.img of=/dev/sdb bs=1k seek=128; sync
|
||||||
|
|
||||||
|
- Jumper settings:
|
||||||
|
|
||||||
|
SW7: 1 0 1 0
|
||||||
|
|
||||||
|
where 0 means bottom position and 1 means top position (from the
|
||||||
|
switch label numbers reference).
|
||||||
|
|
||||||
|
- Connect the USB cable between the EVK and the PC for the console.
|
||||||
|
(The USB console connector is the one close the ethernet connector)
|
||||||
|
|
||||||
|
- Insert the micro SD card in the board, power it up and U-Boot messages should
|
||||||
|
come up.
|
36
board/freescale/imxrt1050-evk/imximage.cfg
Normal file
36
board/freescale/imxrt1050-evk/imximage.cfg
Normal file
@ -0,0 +1,36 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define __ASSEMBLY__
|
||||||
|
#include <config.h>
|
||||||
|
|
||||||
|
/* image version */
|
||||||
|
|
||||||
|
IMAGE_VERSION 2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Boot Device : one of
|
||||||
|
* spi/sd/nand/onenand, qspi/nor
|
||||||
|
*/
|
||||||
|
|
||||||
|
BOOT_FROM sd
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Device Configuration Data (DCD)
|
||||||
|
*
|
||||||
|
* Each entry must have the format:
|
||||||
|
* Addr-type Address Value
|
||||||
|
*
|
||||||
|
* where:
|
||||||
|
* Addr-type register length (1,2 or 4 bytes)
|
||||||
|
* Address absolute address of the register
|
||||||
|
* value value to be stored in the register
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Set all FlexRAM as OCRAM(01b) */
|
||||||
|
DATA 4 0x400AC044 0x55555555
|
||||||
|
/* Use FLEXRAM_BANK_CFG to config FlexRAM */
|
||||||
|
SET_BIT 4 0x400AC040 0x4
|
81
board/freescale/imxrt1050-evk/imxrt1050-evk.c
Normal file
81
board/freescale/imxrt1050-evk/imxrt1050-evk.c
Normal file
@ -0,0 +1,81 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <ram.h>
|
||||||
|
#include <spl.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/armv7m.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
int dram_init(void)
|
||||||
|
{
|
||||||
|
#ifndef CONFIG_SUPPORT_SPL
|
||||||
|
int rv;
|
||||||
|
struct udevice *dev;
|
||||||
|
|
||||||
|
rv = uclass_get_device(UCLASS_RAM, 0, &dev);
|
||||||
|
if (rv) {
|
||||||
|
debug("DRAM init failed: %d\n", rv);
|
||||||
|
return rv;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
return fdtdec_setup_mem_size_base();
|
||||||
|
}
|
||||||
|
|
||||||
|
int dram_init_banksize(void)
|
||||||
|
{
|
||||||
|
return fdtdec_setup_memory_banksize();
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_SPL_BUILD
|
||||||
|
#ifdef CONFIG_SPL_OS_BOOT
|
||||||
|
int spl_start_uboot(void)
|
||||||
|
{
|
||||||
|
debug("SPL: booting kernel\n");
|
||||||
|
/* break into full u-boot on 'c' */
|
||||||
|
return serial_tstc() && serial_getc() == 'c';
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
int spl_dram_init(void)
|
||||||
|
{
|
||||||
|
struct udevice *dev;
|
||||||
|
int rv;
|
||||||
|
|
||||||
|
rv = uclass_get_device(UCLASS_RAM, 0, &dev);
|
||||||
|
if (rv)
|
||||||
|
debug("DRAM init failed: %d\n", rv);
|
||||||
|
return rv;
|
||||||
|
}
|
||||||
|
|
||||||
|
void spl_board_init(void)
|
||||||
|
{
|
||||||
|
spl_dram_init();
|
||||||
|
preloader_console_init();
|
||||||
|
arch_cpu_init(); /* to configure mpu for sdram rw permissions */
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 spl_boot_device(void)
|
||||||
|
{
|
||||||
|
return BOOT_DEVICE_MMC1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
u32 get_board_rev(void)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_init(void)
|
||||||
|
{
|
||||||
|
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
@ -36,14 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||||
|
|
||||||
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
|
||||||
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
|
|
||||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
|
||||||
|
|
||||||
#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
|
||||||
PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
|
|
||||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
|
||||||
|
|
||||||
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||||
@ -112,67 +104,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
|
|||||||
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||||
};
|
};
|
||||||
|
|
||||||
static iomux_v3_cfg_t const usdhc1_pads[] = {
|
|
||||||
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
|
|
||||||
/* VSELECT */
|
|
||||||
MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
/* CD */
|
|
||||||
MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
||||||
/* RST_B */
|
|
||||||
MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* mx6ul_14x14_evk board default supports sd card. If want to use
|
|
||||||
* EMMC, need to do board rework for sd2.
|
|
||||||
* Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
|
|
||||||
* emmc, need to define this macro.
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
|
|
||||||
static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
|
|
||||||
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
|
|
||||||
/*
|
|
||||||
* RST_B
|
|
||||||
*/
|
|
||||||
MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
||||||
};
|
|
||||||
#else
|
|
||||||
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
|
||||||
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The evk board uses DAT3 to detect CD card plugin,
|
|
||||||
* in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
|
|
||||||
*/
|
|
||||||
static iomux_v3_cfg_t const usdhc2_cd_pad =
|
|
||||||
MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
|
|
||||||
|
|
||||||
static iomux_v3_cfg_t const usdhc2_dat3_pad =
|
|
||||||
MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
|
|
||||||
MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static void setup_iomux_uart(void)
|
static void setup_iomux_uart(void)
|
||||||
{
|
{
|
||||||
@ -189,101 +120,35 @@ static int board_qspi_init(void)
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_FSL_ESDHC_IMX
|
#ifdef CONFIG_SPL_BUILD
|
||||||
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
|
||||||
{USDHC1_BASE_ADDR, 0, 4},
|
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||||
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
|
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
|
||||||
{USDHC2_BASE_ADDR, 0, 8},
|
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||||
#else
|
|
||||||
{USDHC2_BASE_ADDR, 0, 4},
|
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
||||||
#endif
|
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
};
|
};
|
||||||
|
|
||||||
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
|
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
||||||
#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
|
{USDHC2_BASE_ADDR, 0, 4},
|
||||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
|
};
|
||||||
#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
|
|
||||||
|
|
||||||
int board_mmc_getcd(struct mmc *mmc)
|
int board_mmc_getcd(struct mmc *mmc)
|
||||||
{
|
{
|
||||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
return 1;
|
||||||
int ret = 0;
|
|
||||||
|
|
||||||
switch (cfg->esdhc_base) {
|
|
||||||
case USDHC1_BASE_ADDR:
|
|
||||||
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
|
||||||
break;
|
|
||||||
case USDHC2_BASE_ADDR:
|
|
||||||
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
|
|
||||||
ret = 1;
|
|
||||||
#else
|
|
||||||
imx_iomux_v3_setup_pad(usdhc2_cd_pad);
|
|
||||||
gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
|
|
||||||
gpio_direction_input(USDHC2_CD_GPIO);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Since it is the DAT3 pin, this pin is pulled to
|
|
||||||
* low voltage if no card
|
|
||||||
*/
|
|
||||||
ret = gpio_get_value(USDHC2_CD_GPIO);
|
|
||||||
|
|
||||||
imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
|
|
||||||
#endif
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int board_mmc_init(bd_t *bis)
|
int board_mmc_init(bd_t *bis)
|
||||||
{
|
{
|
||||||
int i, ret;
|
imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
||||||
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||||
/*
|
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
||||||
* According to the board_mmc_init() the following map is done:
|
|
||||||
* (U-Boot device node) (Physical Port)
|
|
||||||
* mmc0 USDHC1
|
|
||||||
* mmc1 USDHC2
|
|
||||||
*/
|
|
||||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
|
||||||
switch (i) {
|
|
||||||
case 0:
|
|
||||||
imx_iomux_v3_setup_multiple_pads(
|
|
||||||
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
|
|
||||||
gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
|
|
||||||
gpio_direction_input(USDHC1_CD_GPIO);
|
|
||||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
|
||||||
|
|
||||||
gpio_direction_output(USDHC1_PWR_GPIO, 0);
|
|
||||||
udelay(500);
|
|
||||||
gpio_direction_output(USDHC1_PWR_GPIO, 1);
|
|
||||||
break;
|
|
||||||
case 1:
|
|
||||||
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
|
|
||||||
imx_iomux_v3_setup_multiple_pads(
|
|
||||||
usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
|
|
||||||
#else
|
|
||||||
imx_iomux_v3_setup_multiple_pads(
|
|
||||||
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
|
||||||
#endif
|
|
||||||
gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
|
|
||||||
gpio_direction_output(USDHC2_PWR_GPIO, 0);
|
|
||||||
udelay(500);
|
|
||||||
gpio_direction_output(USDHC2_PWR_GPIO, 1);
|
|
||||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
|
||||||
if (ret) {
|
|
||||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
25
board/siemens/capricorn/Kconfig
Normal file
25
board/siemens/capricorn/Kconfig
Normal file
@ -0,0 +1,25 @@
|
|||||||
|
if TARGET_GIEDI
|
||||||
|
|
||||||
|
config SYS_BOARD
|
||||||
|
default "capricorn"
|
||||||
|
|
||||||
|
config SYS_VENDOR
|
||||||
|
default "siemens"
|
||||||
|
|
||||||
|
config SYS_CONFIG_NAME
|
||||||
|
default "giedi"
|
||||||
|
|
||||||
|
endif
|
||||||
|
|
||||||
|
if TARGET_DENEB
|
||||||
|
|
||||||
|
config SYS_BOARD
|
||||||
|
default "capricorn"
|
||||||
|
|
||||||
|
config SYS_VENDOR
|
||||||
|
default "siemens"
|
||||||
|
|
||||||
|
config SYS_CONFIG_NAME
|
||||||
|
default "deneb"
|
||||||
|
|
||||||
|
endif
|
11
board/siemens/capricorn/MAINTAINERS
Normal file
11
board/siemens/capricorn/MAINTAINERS
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
CAPRICORN BOARD
|
||||||
|
M: Anatolij Gustschin <agust@denx.de>
|
||||||
|
S: Maintained
|
||||||
|
F: board/siemens/capricorn/
|
||||||
|
F: include/configs/capricorn-common.h
|
||||||
|
F: include/configs/deneb.h
|
||||||
|
F: include/configs/giedi.h
|
||||||
|
F: include/configs/siemens-ccp-common.h
|
||||||
|
F: include/configs/siemens-env-common.h
|
||||||
|
F: configs/deneb_defconfig
|
||||||
|
F: configs/giedi_defconfig
|
12
board/siemens/capricorn/Makefile
Normal file
12
board/siemens/capricorn/Makefile
Normal file
@ -0,0 +1,12 @@
|
|||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
# Copyright 2019 Siemens AG
|
||||||
|
#
|
||||||
|
|
||||||
|
obj-y += board.o
|
||||||
|
|
||||||
|
ifdef CONFIG_SPL_BUILD
|
||||||
|
obj-y += spl.o
|
||||||
|
else
|
||||||
|
obj-y += ../common/factoryset.o
|
||||||
|
endif
|
448
board/siemens/capricorn/board.c
Normal file
448
board/siemens/capricorn/board.c
Normal file
@ -0,0 +1,448 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright 2017-2019 NXP
|
||||||
|
*
|
||||||
|
* Copyright 2019 Siemens AG
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#include <common.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <netdev.h>
|
||||||
|
#include <env_internal.h>
|
||||||
|
#include <fsl_esdhc_imx.h>
|
||||||
|
#include <i2c.h>
|
||||||
|
#include <led.h>
|
||||||
|
#include <pca953x.h>
|
||||||
|
#include <power-domain.h>
|
||||||
|
#include <asm/gpio.h>
|
||||||
|
#include <asm/arch/imx8-pins.h>
|
||||||
|
#include <asm/arch/iomux.h>
|
||||||
|
#include <asm/arch/sci/sci.h>
|
||||||
|
#include <asm/arch/sys_proto.h>
|
||||||
|
#ifndef CONFIG_SPL
|
||||||
|
#include <asm/arch-imx8/clock.h>
|
||||||
|
#endif
|
||||||
|
#include "../common/factoryset.h"
|
||||||
|
|
||||||
|
#define GPIO_PAD_CTRL \
|
||||||
|
((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
|
||||||
|
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||||
|
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||||
|
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||||
|
|
||||||
|
#define ENET_NORMAL_PAD_CTRL \
|
||||||
|
((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
|
||||||
|
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||||
|
(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
|
||||||
|
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||||
|
|
||||||
|
#define UART_PAD_CTRL \
|
||||||
|
((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
|
||||||
|
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||||
|
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||||
|
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||||
|
|
||||||
|
static iomux_cfg_t uart2_pads[] = {
|
||||||
|
SC_P_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||||
|
SC_P_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||||
|
};
|
||||||
|
|
||||||
|
static void setup_iomux_uart(void)
|
||||||
|
{
|
||||||
|
imx8_iomux_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_early_init_f(void)
|
||||||
|
{
|
||||||
|
/* Set UART clock root to 80 MHz */
|
||||||
|
sc_pm_clock_rate_t rate = SC_80MHZ;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = sc_pm_setup_uart(SC_R_UART_0, rate);
|
||||||
|
ret |= sc_pm_setup_uart(SC_R_UART_2, rate);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
setup_iomux_uart();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define ENET_PHY_RESET IMX_GPIO_NR(0, 3)
|
||||||
|
#define ENET_TEST_1 IMX_GPIO_NR(0, 8)
|
||||||
|
#define ENET_TEST_2 IMX_GPIO_NR(0, 9)
|
||||||
|
|
||||||
|
/*#define ETH_IO_TEST*/
|
||||||
|
static iomux_cfg_t enet_reset[] = {
|
||||||
|
SC_P_ESAI0_SCKT | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
|
||||||
|
#ifdef ETH_IO_TEST
|
||||||
|
/* GPIO0.IO08 MODE3: TXD0 */
|
||||||
|
SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(4) |
|
||||||
|
MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
|
||||||
|
/* GPIO0.IO09 MODE3: TXD1 */
|
||||||
|
SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(4) |
|
||||||
|
MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
static void enet_device_phy_reset(void)
|
||||||
|
{
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
imx8_iomux_setup_multiple_pads(enet_reset, ARRAY_SIZE(enet_reset));
|
||||||
|
|
||||||
|
ret = gpio_request(ENET_PHY_RESET, "enet_phy_reset");
|
||||||
|
if (!ret) {
|
||||||
|
gpio_direction_output(ENET_PHY_RESET, 1);
|
||||||
|
gpio_set_value(ENET_PHY_RESET, 0);
|
||||||
|
/* SMSC9303 TRM chapter 14.5.2 */
|
||||||
|
udelay(200);
|
||||||
|
gpio_set_value(ENET_PHY_RESET, 1);
|
||||||
|
} else {
|
||||||
|
printf("ENET RESET failed!\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef ETH_IO_TEST
|
||||||
|
ret = gpio_request(ENET_TEST_1, "enet_test1");
|
||||||
|
if (!ret) {
|
||||||
|
int i;
|
||||||
|
|
||||||
|
printf("ENET TEST 1!\n");
|
||||||
|
for (i = 0; i < 20; i++) {
|
||||||
|
gpio_direction_output(ENET_TEST_1, 1);
|
||||||
|
gpio_set_value(ENET_TEST_1, 0);
|
||||||
|
udelay(50);
|
||||||
|
gpio_set_value(ENET_TEST_1, 1);
|
||||||
|
udelay(50);
|
||||||
|
}
|
||||||
|
gpio_free(ENET_TEST_1);
|
||||||
|
} else {
|
||||||
|
printf("GPIO for ENET TEST 1 failed!\n");
|
||||||
|
}
|
||||||
|
ret = gpio_request(ENET_TEST_2, "enet_test2");
|
||||||
|
if (!ret) {
|
||||||
|
int i;
|
||||||
|
|
||||||
|
printf("ENET TEST 2!\n");
|
||||||
|
for (i = 0; i < 20; i++) {
|
||||||
|
gpio_direction_output(ENET_TEST_2, 1);
|
||||||
|
gpio_set_value(ENET_TEST_2, 0);
|
||||||
|
udelay(50);
|
||||||
|
gpio_set_value(ENET_TEST_2, 1);
|
||||||
|
udelay(50);
|
||||||
|
}
|
||||||
|
gpio_free(ENET_TEST_2);
|
||||||
|
} else {
|
||||||
|
printf("GPIO for ENET TEST 2 failed!\n");
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
int setup_gpr_fec(void)
|
||||||
|
{
|
||||||
|
sc_ipc_t ipc_handle = -1;
|
||||||
|
sc_err_t err = 0;
|
||||||
|
unsigned int test;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TX_CLK_SEL: it controls a mux between clock coming from the pad 50M
|
||||||
|
* input pin and clock generated internally to connectivity subsystem
|
||||||
|
* 0: internal clock
|
||||||
|
* 1: external clock ---> your choice for RMII
|
||||||
|
*
|
||||||
|
* CLKDIV_SEL: it controls a div by 2 on the internal clock path à
|
||||||
|
* it should be don’t care when using external clock
|
||||||
|
* 0: non-divided clock
|
||||||
|
* 1: clock divided by 2
|
||||||
|
* 50_DISABLE or 125_DISABLE:
|
||||||
|
* it’s used to disable the clock tree going outside the chip
|
||||||
|
* when reference clock is generated internally.
|
||||||
|
* It should be don’t care when reference clock is provided
|
||||||
|
* externally.
|
||||||
|
* 0: clock is enabled
|
||||||
|
* 1: clock is disabled
|
||||||
|
*
|
||||||
|
* SC_C_TXCLK = 24,
|
||||||
|
* SC_C_CLKDIV = 25,
|
||||||
|
* SC_C_DISABLE_50 = 26,
|
||||||
|
* SC_C_DISABLE_125 = 27,
|
||||||
|
*/
|
||||||
|
|
||||||
|
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, 1);
|
||||||
|
if (err != SC_ERR_NONE)
|
||||||
|
printf("Error in setting up SC_C %d\n\r", SC_C_TXCLK);
|
||||||
|
|
||||||
|
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
|
||||||
|
debug("TEST SC_C %d-->%d\n\r", SC_C_TXCLK, test);
|
||||||
|
|
||||||
|
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, 0);
|
||||||
|
if (err != SC_ERR_NONE)
|
||||||
|
printf("Error in setting up SC_C %d\n\r", SC_C_CLKDIV);
|
||||||
|
|
||||||
|
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, &test);
|
||||||
|
debug("TEST SC_C %d-->%d\n\r", SC_C_CLKDIV, test);
|
||||||
|
|
||||||
|
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_50, 0);
|
||||||
|
if (err != SC_ERR_NONE)
|
||||||
|
printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_50);
|
||||||
|
|
||||||
|
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
|
||||||
|
debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_50, test);
|
||||||
|
|
||||||
|
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_125, 1);
|
||||||
|
if (err != SC_ERR_NONE)
|
||||||
|
printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_125);
|
||||||
|
|
||||||
|
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
|
||||||
|
debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_125, test);
|
||||||
|
|
||||||
|
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, 1);
|
||||||
|
if (err != SC_ERR_NONE)
|
||||||
|
printf("Error in setting up SC_C %d\n\r", SC_C_SEL_125);
|
||||||
|
|
||||||
|
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, &test);
|
||||||
|
debug("TEST SC_C %d-->%d\n\r", SC_C_SEL_125, test);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if IS_ENABLED(CONFIG_FEC_MXC)
|
||||||
|
#include <miiphy.h>
|
||||||
|
int board_phy_config(struct phy_device *phydev)
|
||||||
|
{
|
||||||
|
if (phydev->drv->config)
|
||||||
|
phydev->drv->config(phydev);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static int setup_fec(void)
|
||||||
|
{
|
||||||
|
setup_gpr_fec();
|
||||||
|
/* Reset ENET PHY */
|
||||||
|
enet_device_phy_reset();
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void reset_cpu(ulong addr)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifndef CONFIG_SPL_BUILD
|
||||||
|
/* LED's */
|
||||||
|
static int board_led_init(void)
|
||||||
|
{
|
||||||
|
struct udevice *bus, *dev;
|
||||||
|
u8 pca_led[2] = { 0x00, 0x00 };
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
/* init all GPIO LED's */
|
||||||
|
if (IS_ENABLED(CONFIG_LED))
|
||||||
|
led_default_state();
|
||||||
|
|
||||||
|
/* enable all leds on PCA9552 */
|
||||||
|
ret = uclass_get_device_by_seq(UCLASS_I2C, PCA9552_1_I2C_BUS, &bus);
|
||||||
|
if (ret) {
|
||||||
|
printf("ERROR: I2C get %d\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = dm_i2c_probe(bus, PCA9552_1_I2C_ADDR, 0, &dev);
|
||||||
|
if (ret) {
|
||||||
|
printf("ERROR: PCA9552 probe failed\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = dm_i2c_write(dev, 0x16, pca_led, sizeof(pca_led));
|
||||||
|
if (ret) {
|
||||||
|
printf("ERROR: PCA9552 write failed\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
mdelay(1);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
#endif /* !CONFIG_SPL_BUILD */
|
||||||
|
|
||||||
|
int checkboard(void)
|
||||||
|
{
|
||||||
|
puts("Board: Capricorn\n");
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Running build_info() doesn't work with current SCFW blob.
|
||||||
|
* Uncomment below call when new blob is available.
|
||||||
|
*/
|
||||||
|
/*build_info();*/
|
||||||
|
|
||||||
|
print_bootinfo();
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_init(void)
|
||||||
|
{
|
||||||
|
setup_fec();
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_OF_BOARD_SETUP
|
||||||
|
int ft_board_setup(void *blob, bd_t *bd)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
int board_mmc_get_env_dev(int devno)
|
||||||
|
{
|
||||||
|
return devno;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int check_mmc_autodetect(void)
|
||||||
|
{
|
||||||
|
char *autodetect_str = env_get("mmcautodetect");
|
||||||
|
|
||||||
|
if (autodetect_str && (strcmp(autodetect_str, "yes") == 0))
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* This should be defined for each board */
|
||||||
|
__weak int mmc_map_to_kernel_blk(int dev_no)
|
||||||
|
{
|
||||||
|
return dev_no;
|
||||||
|
}
|
||||||
|
|
||||||
|
void board_late_mmc_env_init(void)
|
||||||
|
{
|
||||||
|
char cmd[32];
|
||||||
|
char mmcblk[32];
|
||||||
|
u32 dev_no = mmc_get_env_dev();
|
||||||
|
|
||||||
|
if (!check_mmc_autodetect())
|
||||||
|
return;
|
||||||
|
|
||||||
|
env_set_ulong("mmcdev", dev_no);
|
||||||
|
|
||||||
|
/* Set mmcblk env */
|
||||||
|
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
|
||||||
|
mmc_map_to_kernel_blk(dev_no));
|
||||||
|
env_set("mmcroot", mmcblk);
|
||||||
|
|
||||||
|
sprintf(cmd, "mmc dev %d", dev_no);
|
||||||
|
run_command(cmd, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifndef CONFIG_SPL_BUILD
|
||||||
|
int factoryset_read_eeprom(int i2c_addr);
|
||||||
|
|
||||||
|
static int load_parameters_from_factoryset(void)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = factoryset_read_eeprom(EEPROM_I2C_ADDR);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
return factoryset_env_set();
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_late_init(void)
|
||||||
|
{
|
||||||
|
env_set("sec_boot", "no");
|
||||||
|
#ifdef CONFIG_AHAB_BOOT
|
||||||
|
env_set("sec_boot", "yes");
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||||
|
board_late_mmc_env_init();
|
||||||
|
#endif
|
||||||
|
/* Init LEDs */
|
||||||
|
if (board_led_init())
|
||||||
|
printf("I2C LED init failed\n");
|
||||||
|
|
||||||
|
/* Set environment from factoryset */
|
||||||
|
if (load_parameters_from_factoryset())
|
||||||
|
printf("Loading factoryset parameters failed!\n");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Service button */
|
||||||
|
#define MAX_PIN_NUMBER 128
|
||||||
|
#define BOARD_DEFAULT_BUTTON_GPIO IMX_GPIO_NR(1, 31)
|
||||||
|
|
||||||
|
unsigned char get_button_state(char * const envname, unsigned char def)
|
||||||
|
{
|
||||||
|
int button = 0;
|
||||||
|
int gpio;
|
||||||
|
char *ptr_env;
|
||||||
|
|
||||||
|
/* If button is not found we take default */
|
||||||
|
ptr_env = env_get(envname);
|
||||||
|
if (!ptr_env) {
|
||||||
|
printf("Using default: %u\n", def);
|
||||||
|
gpio = def;
|
||||||
|
} else {
|
||||||
|
gpio = (unsigned char)simple_strtoul(ptr_env, NULL, 0);
|
||||||
|
if (gpio > MAX_PIN_NUMBER)
|
||||||
|
gpio = def;
|
||||||
|
}
|
||||||
|
|
||||||
|
gpio_request(gpio, "");
|
||||||
|
gpio_direction_input(gpio);
|
||||||
|
if (gpio_get_value(gpio))
|
||||||
|
button = 1;
|
||||||
|
else
|
||||||
|
button = 0;
|
||||||
|
|
||||||
|
gpio_free(gpio);
|
||||||
|
|
||||||
|
return button;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This command returns the status of the user button on
|
||||||
|
* Input - none
|
||||||
|
* Returns - 1 if button is held down
|
||||||
|
* 0 if button is not held down
|
||||||
|
*/
|
||||||
|
static int
|
||||||
|
do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||||
|
{
|
||||||
|
int button = 0;
|
||||||
|
|
||||||
|
button = get_button_state("button_usr1", BOARD_DEFAULT_BUTTON_GPIO);
|
||||||
|
|
||||||
|
if (argc > 1)
|
||||||
|
printf("Button state: %u\n", button);
|
||||||
|
|
||||||
|
return button;
|
||||||
|
}
|
||||||
|
|
||||||
|
U_BOOT_CMD(
|
||||||
|
usrbutton, CONFIG_SYS_MAXARGS, 2, do_userbutton,
|
||||||
|
"Return the status of user button",
|
||||||
|
"[print]"
|
||||||
|
);
|
||||||
|
|
||||||
|
#define ERST IMX_GPIO_NR(0, 3)
|
||||||
|
|
||||||
|
static int
|
||||||
|
do_eth_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||||
|
{
|
||||||
|
gpio_request(ERST, "ERST");
|
||||||
|
gpio_direction_output(ERST, 0);
|
||||||
|
udelay(200);
|
||||||
|
gpio_set_value(ERST, 1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
U_BOOT_CMD(
|
||||||
|
switch_rst, CONFIG_SYS_MAXARGS, 2, do_eth_reset,
|
||||||
|
"Reset eth phy",
|
||||||
|
"[print]"
|
||||||
|
);
|
||||||
|
#endif /* ! CONFIG_SPL_BUILD */
|
22
board/siemens/capricorn/imximage.cfg
Normal file
22
board/siemens/capricorn/imximage.cfg
Normal file
@ -0,0 +1,22 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright 2018 NXP
|
||||||
|
*
|
||||||
|
* Refer doc/README.imx8image for more details about how-to configure
|
||||||
|
* and create imx8image boot image
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define __ASSEMBLY__
|
||||||
|
|
||||||
|
/* Boot from SD, sector size 0x400 */
|
||||||
|
BOOT_FROM SD 0x400
|
||||||
|
/* SoC type IMX8QX */
|
||||||
|
SOC_TYPE IMX8QX
|
||||||
|
/* Append seco container image */
|
||||||
|
APPEND ahab-container.img
|
||||||
|
/* Create the 2nd container */
|
||||||
|
CONTAINER
|
||||||
|
/* Add scfw image with exec attribute */
|
||||||
|
IMAGE SCU capricorn-scfw-tcm.bin
|
||||||
|
/* Add ATF image with exec attribute */
|
||||||
|
IMAGE A35 spl/u-boot-spl.bin 0x00100000
|
47
board/siemens/capricorn/spl.c
Normal file
47
board/siemens/capricorn/spl.c
Normal file
@ -0,0 +1,47 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright 2018 NXP
|
||||||
|
*
|
||||||
|
* Copyright 2019 Siemens AG
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#include <common.h>
|
||||||
|
#include <spl.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <dm/uclass.h>
|
||||||
|
#include <dm/device.h>
|
||||||
|
#include <dm/uclass-internal.h>
|
||||||
|
#include <dm/device-internal.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
void spl_board_init(void)
|
||||||
|
{
|
||||||
|
struct udevice *dev;
|
||||||
|
|
||||||
|
uclass_find_first_device(UCLASS_MISC, &dev);
|
||||||
|
|
||||||
|
for (; dev; uclass_find_next_device(&dev)) {
|
||||||
|
if (device_probe(dev))
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
arch_cpu_init();
|
||||||
|
|
||||||
|
board_early_init_f();
|
||||||
|
|
||||||
|
timer_init();
|
||||||
|
|
||||||
|
preloader_console_init();
|
||||||
|
}
|
||||||
|
|
||||||
|
void board_init_f(ulong dummy)
|
||||||
|
{
|
||||||
|
/* Clear global data */
|
||||||
|
memset((void *)gd, 0, sizeof(gd_t));
|
||||||
|
|
||||||
|
/* Clear the BSS. */
|
||||||
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||||
|
|
||||||
|
board_init_r(NULL, 0);
|
||||||
|
}
|
13
board/siemens/capricorn/uboot-container.cfg
Normal file
13
board/siemens/capricorn/uboot-container.cfg
Normal file
@ -0,0 +1,13 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright 2019 NXP
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define __ASSEMBLY__
|
||||||
|
|
||||||
|
/* This file is to create a container image could be loaded by SPL */
|
||||||
|
BOOT_FROM SD 0x400
|
||||||
|
SOC_TYPE IMX8QX
|
||||||
|
CONTAINER
|
||||||
|
IMAGE A35 bl31.bin 0x80000000
|
||||||
|
IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE
|
@ -13,7 +13,9 @@
|
|||||||
#include <env_internal.h>
|
#include <env_internal.h>
|
||||||
#include <i2c.h>
|
#include <i2c.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
|
#if !CONFIG_IS_ENABLED(TARGET_GIEDI) && !CONFIG_IS_ENABLED(TARGET_DENEB)
|
||||||
#include <asm/arch/cpu.h>
|
#include <asm/arch/cpu.h>
|
||||||
|
#endif
|
||||||
#include <asm/arch/sys_proto.h>
|
#include <asm/arch/sys_proto.h>
|
||||||
#include <asm/unaligned.h>
|
#include <asm/unaligned.h>
|
||||||
#include <net.h>
|
#include <net.h>
|
||||||
|
@ -16,7 +16,6 @@
|
|||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <i2c.h>
|
#include <i2c.h>
|
||||||
#include <miiphy.h>
|
#include <miiphy.h>
|
||||||
#include <netdev.h>
|
|
||||||
#include <power/pmic.h>
|
#include <power/pmic.h>
|
||||||
#include <power/pfuze3000_pmic.h>
|
#include <power/pfuze3000_pmic.h>
|
||||||
#include "../../freescale/common/pfuze.h"
|
#include "../../freescale/common/pfuze.h"
|
||||||
@ -26,11 +25,6 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||||||
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
|
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
|
||||||
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
|
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
|
||||||
|
|
||||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
|
|
||||||
#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
|
|
||||||
|
|
||||||
#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
|
|
||||||
|
|
||||||
#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
|
#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
|
||||||
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
|
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
|
||||||
|
|
||||||
@ -123,44 +117,6 @@ static iomux_v3_cfg_t const uart5_pads[] = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
#ifdef CONFIG_FEC_MXC
|
#ifdef CONFIG_FEC_MXC
|
||||||
static iomux_v3_cfg_t const fec1_pads[] = {
|
|
||||||
MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
|
||||||
MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
|
||||||
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
||||||
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
||||||
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
||||||
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
||||||
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
||||||
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
||||||
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
|
||||||
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
|
||||||
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
|
||||||
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
|
||||||
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
|
||||||
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
|
||||||
MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
||||||
MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
||||||
};
|
|
||||||
|
|
||||||
#define FEC1_RST_GPIO IMX_GPIO_NR(6, 11)
|
|
||||||
|
|
||||||
static void setup_iomux_fec(void)
|
|
||||||
{
|
|
||||||
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
|
|
||||||
gpio_request(FEC1_RST_GPIO, "phy_rst");
|
|
||||||
gpio_direction_output(FEC1_RST_GPIO, 0);
|
|
||||||
udelay(500);
|
|
||||||
gpio_set_value(FEC1_RST_GPIO, 1);
|
|
||||||
}
|
|
||||||
|
|
||||||
int board_eth_init(bd_t *bis)
|
|
||||||
{
|
|
||||||
setup_iomux_fec();
|
|
||||||
|
|
||||||
return fecmxc_initialize_multi(bis, 0,
|
|
||||||
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
|
||||||
}
|
|
||||||
|
|
||||||
static int setup_fec(void)
|
static int setup_fec(void)
|
||||||
{
|
{
|
||||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
||||||
@ -235,9 +191,7 @@ int board_init(void)
|
|||||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||||
|
|
||||||
#ifdef CONFIG_DM_VIDEO
|
#ifdef CONFIG_DM_VIDEO
|
||||||
|
|
||||||
setup_lcd();
|
setup_lcd();
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_FEC_MXC
|
#ifdef CONFIG_FEC_MXC
|
||||||
setup_fec();
|
setup_fec();
|
||||||
|
@ -363,7 +363,7 @@ int power_init_board(void)
|
|||||||
|
|
||||||
ret = pmic_get("pfuze100@8", &dev);
|
ret = pmic_get("pfuze100@8", &dev);
|
||||||
if (ret < 0) {
|
if (ret < 0) {
|
||||||
printf("pmic_get() ret %d\n", ret);
|
debug("pmic_get() ret %d\n", ret);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -284,9 +284,9 @@ int spl_parse_image_header(struct spl_image_info *spl_image,
|
|||||||
spl_image->entry_point = image_get_ep(header);
|
spl_image->entry_point = image_get_ep(header);
|
||||||
spl_image->size = image_get_data_size(header);
|
spl_image->size = image_get_data_size(header);
|
||||||
} else {
|
} else {
|
||||||
spl_image->entry_point = image_get_load(header);
|
spl_image->entry_point = image_get_ep(header);
|
||||||
/* Load including the header */
|
/* Load including the header */
|
||||||
spl_image->load_addr = spl_image->entry_point -
|
spl_image->load_addr = image_get_load(header) -
|
||||||
header_size;
|
header_size;
|
||||||
spl_image->size = image_get_data_size(header) +
|
spl_image->size = image_get_data_size(header) +
|
||||||
header_size;
|
header_size;
|
||||||
|
103
configs/deneb_defconfig
Normal file
103
configs/deneb_defconfig
Normal file
@ -0,0 +1,103 @@
|
|||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_SPL_SYS_ICACHE_OFF=y
|
||||||
|
CONFIG_SPL_SYS_DCACHE_OFF=y
|
||||||
|
CONFIG_ARCH_IMX8=y
|
||||||
|
CONFIG_SYS_TEXT_BASE=0x80020000
|
||||||
|
CONFIG_SPL_GPIO_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||||
|
CONFIG_SPL_LOAD_IMX_CONTAINER=y
|
||||||
|
CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
|
||||||
|
CONFIG_TARGET_DENEB=y
|
||||||
|
CONFIG_SPL_MMC_SUPPORT=y
|
||||||
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
|
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||||
|
CONFIG_ENV_SIZE=0x2000
|
||||||
|
CONFIG_ENV_OFFSET=0x0
|
||||||
|
CONFIG_NR_DRAM_BANKS=3
|
||||||
|
CONFIG_SPL=y
|
||||||
|
CONFIG_SPL_TEXT_BASE=0x100000
|
||||||
|
CONFIG_OF_BOARD_SETUP=y
|
||||||
|
CONFIG_OF_SYSTEM_SETUP=y
|
||||||
|
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg"
|
||||||
|
CONFIG_BOOTDELAY=3
|
||||||
|
CONFIG_LOG=y
|
||||||
|
CONFIG_SPL_BOARD_INIT=y
|
||||||
|
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||||
|
CONFIG_SPL_SEPARATE_BSS=y
|
||||||
|
CONFIG_SPL_POWER_SUPPORT=y
|
||||||
|
CONFIG_SPL_POWER_DOMAIN=y
|
||||||
|
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||||
|
CONFIG_HUSH_PARSER=y
|
||||||
|
CONFIG_SYS_PROMPT="U-Boot# "
|
||||||
|
CONFIG_AUTOBOOT_KEYED=y
|
||||||
|
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
|
||||||
|
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
|
||||||
|
CONFIG_AUTOBOOT_KEYED_CTRLC=y
|
||||||
|
CONFIG_CMD_CPU=y
|
||||||
|
# CONFIG_CMD_IMPORTENV is not set
|
||||||
|
CONFIG_CMD_CLK=y
|
||||||
|
CONFIG_CMD_DM=y
|
||||||
|
CONFIG_CMD_FUSE=y
|
||||||
|
CONFIG_CMD_GPIO=y
|
||||||
|
CONFIG_CMD_I2C=y
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_DHCP=y
|
||||||
|
CONFIG_CMD_MII=y
|
||||||
|
CONFIG_CMD_PING=y
|
||||||
|
CONFIG_CMD_CACHE=y
|
||||||
|
CONFIG_CMD_EXT2=y
|
||||||
|
CONFIG_CMD_EXT4=y
|
||||||
|
CONFIG_CMD_FAT=y
|
||||||
|
CONFIG_CMD_FS_GENERIC=y
|
||||||
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="imx8-deneb"
|
||||||
|
CONFIG_ENV_IS_IN_MMC=y
|
||||||
|
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||||
|
CONFIG_ENV_OFFSET_REDUND=0x2000
|
||||||
|
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||||
|
CONFIG_NET_RANDOM_ETHADDR=y
|
||||||
|
CONFIG_SPL_DM=y
|
||||||
|
CONFIG_SPL_CLK=y
|
||||||
|
CONFIG_CLK_IMX8=y
|
||||||
|
CONFIG_CPU=y
|
||||||
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_MXC_GPIO=y
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_SYS_I2C_IMX_LPI2C=y
|
||||||
|
CONFIG_LED=y
|
||||||
|
CONFIG_LED_GPIO=y
|
||||||
|
CONFIG_MISC=y
|
||||||
|
CONFIG_DM_MMC=y
|
||||||
|
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||||
|
CONFIG_MMC_IO_VOLTAGE=y
|
||||||
|
CONFIG_MMC_UHS_SUPPORT=y
|
||||||
|
CONFIG_MMC_HS400_SUPPORT=y
|
||||||
|
CONFIG_FSL_USDHC=y
|
||||||
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_MV88E61XX_SWITCH=y
|
||||||
|
CONFIG_MV88E61XX_CPU_PORT=5
|
||||||
|
CONFIG_MV88E61XX_PHY_PORTS=0x7
|
||||||
|
CONFIG_MV88E61XX_FIXED_PORTS=0x0
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_FEC_MXC_SHARE_MDIO=y
|
||||||
|
CONFIG_FEC_MXC_MDIO_BASE=0x5B050000
|
||||||
|
CONFIG_FEC_MXC=y
|
||||||
|
CONFIG_MII=y
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
|
CONFIG_SPL_PINCTRL=y
|
||||||
|
CONFIG_PINCTRL_IMX8=y
|
||||||
|
CONFIG_POWER_DOMAIN=y
|
||||||
|
CONFIG_IMX8_POWER_DOMAIN=y
|
||||||
|
CONFIG_DM_REGULATOR=y
|
||||||
|
CONFIG_DM_REGULATOR_FIXED=y
|
||||||
|
CONFIG_DM_REGULATOR_GPIO=y
|
||||||
|
CONFIG_SPL_DM_REGULATOR_GPIO=y
|
||||||
|
CONFIG_DM_SERIAL=y
|
||||||
|
CONFIG_FSL_LPUART=y
|
||||||
|
CONFIG_DM_THERMAL=y
|
||||||
|
CONFIG_IMX_SCU_THERMAL=y
|
||||||
|
# CONFIG_SPL_WDT is not set
|
||||||
|
CONFIG_SPL_TINY_MEMSET=y
|
||||||
|
# CONFIG_EFI_LOADER is not set
|
103
configs/giedi_defconfig
Normal file
103
configs/giedi_defconfig
Normal file
@ -0,0 +1,103 @@
|
|||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_SPL_SYS_ICACHE_OFF=y
|
||||||
|
CONFIG_SPL_SYS_DCACHE_OFF=y
|
||||||
|
CONFIG_ARCH_IMX8=y
|
||||||
|
CONFIG_SYS_TEXT_BASE=0x80020000
|
||||||
|
CONFIG_SPL_GPIO_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||||
|
CONFIG_SPL_LOAD_IMX_CONTAINER=y
|
||||||
|
CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
|
||||||
|
CONFIG_TARGET_GIEDI=y
|
||||||
|
CONFIG_SPL_MMC_SUPPORT=y
|
||||||
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
|
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||||
|
CONFIG_ENV_SIZE=0x2000
|
||||||
|
CONFIG_ENV_OFFSET=0x0
|
||||||
|
CONFIG_NR_DRAM_BANKS=3
|
||||||
|
CONFIG_SPL=y
|
||||||
|
CONFIG_SPL_TEXT_BASE=0x100000
|
||||||
|
CONFIG_OF_BOARD_SETUP=y
|
||||||
|
CONFIG_OF_SYSTEM_SETUP=y
|
||||||
|
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg"
|
||||||
|
CONFIG_BOOTDELAY=3
|
||||||
|
CONFIG_LOG=y
|
||||||
|
CONFIG_SPL_BOARD_INIT=y
|
||||||
|
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||||
|
CONFIG_SPL_SEPARATE_BSS=y
|
||||||
|
CONFIG_SPL_POWER_SUPPORT=y
|
||||||
|
CONFIG_SPL_POWER_DOMAIN=y
|
||||||
|
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||||
|
CONFIG_HUSH_PARSER=y
|
||||||
|
CONFIG_SYS_PROMPT="U-Boot# "
|
||||||
|
CONFIG_AUTOBOOT_KEYED=y
|
||||||
|
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
|
||||||
|
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
|
||||||
|
CONFIG_AUTOBOOT_KEYED_CTRLC=y
|
||||||
|
CONFIG_CMD_CPU=y
|
||||||
|
# CONFIG_CMD_IMPORTENV is not set
|
||||||
|
CONFIG_CMD_CLK=y
|
||||||
|
CONFIG_CMD_DM=y
|
||||||
|
CONFIG_CMD_FUSE=y
|
||||||
|
CONFIG_CMD_GPIO=y
|
||||||
|
CONFIG_CMD_I2C=y
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_DHCP=y
|
||||||
|
CONFIG_CMD_MII=y
|
||||||
|
CONFIG_CMD_PING=y
|
||||||
|
CONFIG_CMD_CACHE=y
|
||||||
|
CONFIG_CMD_EXT2=y
|
||||||
|
CONFIG_CMD_EXT4=y
|
||||||
|
CONFIG_CMD_FAT=y
|
||||||
|
CONFIG_CMD_FS_GENERIC=y
|
||||||
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi"
|
||||||
|
CONFIG_ENV_IS_IN_MMC=y
|
||||||
|
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||||
|
CONFIG_ENV_OFFSET_REDUND=0x2000
|
||||||
|
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||||
|
CONFIG_NET_RANDOM_ETHADDR=y
|
||||||
|
CONFIG_SPL_DM=y
|
||||||
|
CONFIG_SPL_CLK=y
|
||||||
|
CONFIG_CLK_IMX8=y
|
||||||
|
CONFIG_CPU=y
|
||||||
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_MXC_GPIO=y
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_SYS_I2C_IMX_LPI2C=y
|
||||||
|
CONFIG_LED=y
|
||||||
|
CONFIG_LED_GPIO=y
|
||||||
|
CONFIG_MISC=y
|
||||||
|
CONFIG_DM_MMC=y
|
||||||
|
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||||
|
CONFIG_MMC_IO_VOLTAGE=y
|
||||||
|
CONFIG_MMC_UHS_SUPPORT=y
|
||||||
|
CONFIG_MMC_HS400_SUPPORT=y
|
||||||
|
CONFIG_FSL_USDHC=y
|
||||||
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_MV88E61XX_SWITCH=y
|
||||||
|
CONFIG_MV88E61XX_CPU_PORT=5
|
||||||
|
CONFIG_MV88E61XX_PHY_PORTS=0x7
|
||||||
|
CONFIG_MV88E61XX_FIXED_PORTS=0x0
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_FEC_MXC_SHARE_MDIO=y
|
||||||
|
CONFIG_FEC_MXC_MDIO_BASE=0x5B050000
|
||||||
|
CONFIG_FEC_MXC=y
|
||||||
|
CONFIG_MII=y
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
|
CONFIG_SPL_PINCTRL=y
|
||||||
|
CONFIG_PINCTRL_IMX8=y
|
||||||
|
CONFIG_POWER_DOMAIN=y
|
||||||
|
CONFIG_IMX8_POWER_DOMAIN=y
|
||||||
|
CONFIG_DM_REGULATOR=y
|
||||||
|
CONFIG_DM_REGULATOR_FIXED=y
|
||||||
|
CONFIG_DM_REGULATOR_GPIO=y
|
||||||
|
CONFIG_SPL_DM_REGULATOR_GPIO=y
|
||||||
|
CONFIG_DM_SERIAL=y
|
||||||
|
CONFIG_FSL_LPUART=y
|
||||||
|
CONFIG_DM_THERMAL=y
|
||||||
|
CONFIG_IMX_SCU_THERMAL=y
|
||||||
|
# CONFIG_SPL_WDT is not set
|
||||||
|
CONFIG_SPL_TINY_MEMSET=y
|
||||||
|
# CONFIG_EFI_LOADER is not set
|
@ -47,6 +47,7 @@ CONFIG_SPL_OF_CONTROL=y
|
|||||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
|
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
|
||||||
CONFIG_ENV_IS_IN_MMC=y
|
CONFIG_ENV_IS_IN_MMC=y
|
||||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||||
|
CONFIG_NET_RANDOM_ETHADDR=y
|
||||||
CONFIG_SPL_DM=y
|
CONFIG_SPL_DM=y
|
||||||
CONFIG_SPL_CLK=y
|
CONFIG_SPL_CLK=y
|
||||||
CONFIG_CLK_IMX8=y
|
CONFIG_CLK_IMX8=y
|
||||||
|
69
configs/imxrt1050-evk_defconfig
Normal file
69
configs/imxrt1050-evk_defconfig
Normal file
@ -0,0 +1,69 @@
|
|||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_SYS_ICACHE_OFF=y
|
||||||
|
CONFIG_SYS_DCACHE_OFF=y
|
||||||
|
CONFIG_ARCH_IMXRT=y
|
||||||
|
CONFIG_SYS_TEXT_BASE=0x80002000
|
||||||
|
CONFIG_SPL_GPIO_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||||
|
CONFIG_ENV_OFFSET=0x80000
|
||||||
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_TARGET_IMXRT1050_EVK=y
|
||||||
|
CONFIG_SPL_MMC_SUPPORT=y
|
||||||
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
|
CONFIG_SPL_SIZE_LIMIT=131072
|
||||||
|
CONFIG_SPL=y
|
||||||
|
CONFIG_SPL_TEXT_BASE=0x20209000
|
||||||
|
CONFIG_DISTRO_DEFAULTS=y
|
||||||
|
CONFIG_SD_BOOT=y
|
||||||
|
# CONFIG_USE_BOOTCOMMAND is not set
|
||||||
|
# CONFIG_DISPLAY_CPUINFO is not set
|
||||||
|
CONFIG_SPL_BOARD_INIT=y
|
||||||
|
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||||
|
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||||
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||||
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
|
||||||
|
# CONFIG_SPL_CRC32_SUPPORT is not set
|
||||||
|
# CONFIG_SPL_DM_GPIO is not set
|
||||||
|
# CONFIG_BOOTM_NETBSD is not set
|
||||||
|
# CONFIG_BOOTM_PLAN9 is not set
|
||||||
|
# CONFIG_BOOTM_RTEMS is not set
|
||||||
|
# CONFIG_BOOTM_VXWORKS is not set
|
||||||
|
# CONFIG_CMD_MII is not set
|
||||||
|
# CONFIG_DOS_PARTITION is not set
|
||||||
|
# CONFIG_ISO_PARTITION is not set
|
||||||
|
# CONFIG_EFI_PARTITION is not set
|
||||||
|
CONFIG_OF_CONTROL=y
|
||||||
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
|
||||||
|
CONFIG_ENV_IS_NOWHERE=y
|
||||||
|
CONFIG_ENV_IS_IN_MMC=y
|
||||||
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||||
|
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||||
|
CONFIG_TFTP_BLOCKSIZE=512
|
||||||
|
CONFIG_SPL_DM=y
|
||||||
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||||
|
# CONFIG_OF_TRANSLATE is not set
|
||||||
|
CONFIG_SPL_CLK_COMPOSITE_CCF=y
|
||||||
|
CONFIG_CLK_COMPOSITE_CCF=y
|
||||||
|
CONFIG_SPL_CLK_IMXRT1050=y
|
||||||
|
CONFIG_CLK_IMXRT1050=y
|
||||||
|
CONFIG_MXC_GPIO=y
|
||||||
|
# CONFIG_INPUT is not set
|
||||||
|
CONFIG_DM_MMC=y
|
||||||
|
CONFIG_FSL_USDHC=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
|
CONFIG_SPL_PINCTRL=y
|
||||||
|
CONFIG_PINCTRL_IMXRT=y
|
||||||
|
CONFIG_RAM=y
|
||||||
|
CONFIG_SPL_RAM=y
|
||||||
|
CONFIG_IMXRT_SDRAM=y
|
||||||
|
CONFIG_FSL_LPUART=y
|
||||||
|
CONFIG_TIMER=y
|
||||||
|
CONFIG_SPL_TIMER=y
|
||||||
|
CONFIG_SHA1=y
|
||||||
|
CONFIG_SHA256=y
|
||||||
|
CONFIG_HEXDUMP=y
|
@ -59,6 +59,11 @@ CONFIG_SUPPORT_EMMC_BOOT=y
|
|||||||
CONFIG_FSL_USDHC=y
|
CONFIG_FSL_USDHC=y
|
||||||
CONFIG_MTD=y
|
CONFIG_MTD=y
|
||||||
CONFIG_PHYLIB=y
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_PHY_ATHEROS=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_DM_MDIO=y
|
||||||
|
CONFIG_FEC_MXC=y
|
||||||
|
CONFIG_RGMII=y
|
||||||
CONFIG_MII=y
|
CONFIG_MII=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
CONFIG_PINCTRL_IMX7=y
|
CONFIG_PINCTRL_IMX7=y
|
||||||
|
@ -59,6 +59,11 @@ CONFIG_SUPPORT_EMMC_BOOT=y
|
|||||||
CONFIG_FSL_USDHC=y
|
CONFIG_FSL_USDHC=y
|
||||||
CONFIG_MTD=y
|
CONFIG_MTD=y
|
||||||
CONFIG_PHYLIB=y
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_PHY_ATHEROS=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_DM_MDIO=y
|
||||||
|
CONFIG_FEC_MXC=y
|
||||||
|
CONFIG_RGMII=y
|
||||||
CONFIG_MII=y
|
CONFIG_MII=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
CONFIG_PINCTRL_IMX7=y
|
CONFIG_PINCTRL_IMX7=y
|
||||||
|
@ -50,6 +50,11 @@ CONFIG_DM_MMC=y
|
|||||||
CONFIG_FSL_USDHC=y
|
CONFIG_FSL_USDHC=y
|
||||||
CONFIG_MTD=y
|
CONFIG_MTD=y
|
||||||
CONFIG_PHYLIB=y
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_PHY_ATHEROS=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_DM_MDIO=y
|
||||||
|
CONFIG_FEC_MXC=y
|
||||||
|
CONFIG_RGMII=y
|
||||||
CONFIG_MII=y
|
CONFIG_MII=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
CONFIG_PINCTRL_IMX7=y
|
CONFIG_PINCTRL_IMX7=y
|
||||||
@ -64,9 +69,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
|
|||||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
|
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
|
||||||
CONFIG_CI_UDC=y
|
CONFIG_CI_UDC=y
|
||||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||||
CONFIG_USB_ETHER=y
|
|
||||||
CONFIG_USB_ETH_CDC=y
|
|
||||||
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
|
|
||||||
CONFIG_DM_VIDEO=y
|
CONFIG_DM_VIDEO=y
|
||||||
CONFIG_VIDEO_BPP8=y
|
CONFIG_VIDEO_BPP8=y
|
||||||
CONFIG_VIDEO_BPP16=y
|
CONFIG_VIDEO_BPP16=y
|
||||||
|
@ -59,6 +59,11 @@ CONFIG_SUPPORT_EMMC_BOOT=y
|
|||||||
CONFIG_FSL_USDHC=y
|
CONFIG_FSL_USDHC=y
|
||||||
CONFIG_MTD=y
|
CONFIG_MTD=y
|
||||||
CONFIG_PHYLIB=y
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_PHY_ATHEROS=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_DM_MDIO=y
|
||||||
|
CONFIG_FEC_MXC=y
|
||||||
|
CONFIG_RGMII=y
|
||||||
CONFIG_MII=y
|
CONFIG_MII=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
CONFIG_PINCTRL_IMX7=y
|
CONFIG_PINCTRL_IMX7=y
|
||||||
|
@ -59,6 +59,11 @@ CONFIG_SUPPORT_EMMC_BOOT=y
|
|||||||
CONFIG_FSL_USDHC=y
|
CONFIG_FSL_USDHC=y
|
||||||
CONFIG_MTD=y
|
CONFIG_MTD=y
|
||||||
CONFIG_PHYLIB=y
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_PHY_ATHEROS=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_DM_MDIO=y
|
||||||
|
CONFIG_FEC_MXC=y
|
||||||
|
CONFIG_RGMII=y
|
||||||
CONFIG_MII=y
|
CONFIG_MII=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
CONFIG_PINCTRL_IMX7=y
|
CONFIG_PINCTRL_IMX7=y
|
||||||
|
@ -59,6 +59,11 @@ CONFIG_SUPPORT_EMMC_BOOT=y
|
|||||||
CONFIG_FSL_USDHC=y
|
CONFIG_FSL_USDHC=y
|
||||||
CONFIG_MTD=y
|
CONFIG_MTD=y
|
||||||
CONFIG_PHYLIB=y
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_PHY_ATHEROS=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_DM_MDIO=y
|
||||||
|
CONFIG_FEC_MXC=y
|
||||||
|
CONFIG_RGMII=y
|
||||||
CONFIG_MII=y
|
CONFIG_MII=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
CONFIG_PINCTRL_IMX7=y
|
CONFIG_PINCTRL_IMX7=y
|
||||||
|
@ -68,3 +68,19 @@ config CLK_IMX8MP
|
|||||||
select CLK_CCF
|
select CLK_CCF
|
||||||
help
|
help
|
||||||
This enables support clock driver for i.MX8MP platforms.
|
This enables support clock driver for i.MX8MP platforms.
|
||||||
|
|
||||||
|
config SPL_CLK_IMXRT1050
|
||||||
|
bool "SPL clock support for i.MXRT1050"
|
||||||
|
depends on ARCH_IMXRT && SPL
|
||||||
|
select SPL_CLK
|
||||||
|
select SPL_CLK_CCF
|
||||||
|
help
|
||||||
|
This enables SPL DM/DTS support for clock driver in i.MXRT1050
|
||||||
|
|
||||||
|
config CLK_IMXRT1050
|
||||||
|
bool "Clock support for i.MXRT1050"
|
||||||
|
depends on ARCH_IMXRT
|
||||||
|
select CLK
|
||||||
|
select CLK_CCF
|
||||||
|
help
|
||||||
|
This enables support clock driver for i.MXRT1050 platforms.
|
||||||
|
@ -16,3 +16,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \
|
|||||||
clk-composite-8m.o
|
clk-composite-8m.o
|
||||||
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
|
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
|
||||||
clk-composite-8m.o
|
clk-composite-8m.o
|
||||||
|
|
||||||
|
obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
|
||||||
|
@ -56,18 +56,22 @@ ulong imx8_clk_get_rate(struct clk *clk)
|
|||||||
pm_clk = SC_PM_CLK_CPU;
|
pm_clk = SC_PM_CLK_CPU;
|
||||||
break;
|
break;
|
||||||
case IMX8QXP_I2C0_CLK:
|
case IMX8QXP_I2C0_CLK:
|
||||||
|
case IMX8QXP_I2C0_IPG_CLK:
|
||||||
resource = SC_R_I2C_0;
|
resource = SC_R_I2C_0;
|
||||||
pm_clk = SC_PM_CLK_PER;
|
pm_clk = SC_PM_CLK_PER;
|
||||||
break;
|
break;
|
||||||
case IMX8QXP_I2C1_CLK:
|
case IMX8QXP_I2C1_CLK:
|
||||||
|
case IMX8QXP_I2C1_IPG_CLK:
|
||||||
resource = SC_R_I2C_1;
|
resource = SC_R_I2C_1;
|
||||||
pm_clk = SC_PM_CLK_PER;
|
pm_clk = SC_PM_CLK_PER;
|
||||||
break;
|
break;
|
||||||
case IMX8QXP_I2C2_CLK:
|
case IMX8QXP_I2C2_CLK:
|
||||||
|
case IMX8QXP_I2C2_IPG_CLK:
|
||||||
resource = SC_R_I2C_2;
|
resource = SC_R_I2C_2;
|
||||||
pm_clk = SC_PM_CLK_PER;
|
pm_clk = SC_PM_CLK_PER;
|
||||||
break;
|
break;
|
||||||
case IMX8QXP_I2C3_CLK:
|
case IMX8QXP_I2C3_CLK:
|
||||||
|
case IMX8QXP_I2C3_IPG_CLK:
|
||||||
resource = SC_R_I2C_3;
|
resource = SC_R_I2C_3;
|
||||||
pm_clk = SC_PM_CLK_PER;
|
pm_clk = SC_PM_CLK_PER;
|
||||||
break;
|
break;
|
||||||
@ -145,18 +149,22 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
|
|||||||
|
|
||||||
switch (clk->id) {
|
switch (clk->id) {
|
||||||
case IMX8QXP_I2C0_CLK:
|
case IMX8QXP_I2C0_CLK:
|
||||||
|
case IMX8QXP_I2C0_IPG_CLK:
|
||||||
resource = SC_R_I2C_0;
|
resource = SC_R_I2C_0;
|
||||||
pm_clk = SC_PM_CLK_PER;
|
pm_clk = SC_PM_CLK_PER;
|
||||||
break;
|
break;
|
||||||
case IMX8QXP_I2C1_CLK:
|
case IMX8QXP_I2C1_CLK:
|
||||||
|
case IMX8QXP_I2C1_IPG_CLK:
|
||||||
resource = SC_R_I2C_1;
|
resource = SC_R_I2C_1;
|
||||||
pm_clk = SC_PM_CLK_PER;
|
pm_clk = SC_PM_CLK_PER;
|
||||||
break;
|
break;
|
||||||
case IMX8QXP_I2C2_CLK:
|
case IMX8QXP_I2C2_CLK:
|
||||||
|
case IMX8QXP_I2C2_IPG_CLK:
|
||||||
resource = SC_R_I2C_2;
|
resource = SC_R_I2C_2;
|
||||||
pm_clk = SC_PM_CLK_PER;
|
pm_clk = SC_PM_CLK_PER;
|
||||||
break;
|
break;
|
||||||
case IMX8QXP_I2C3_CLK:
|
case IMX8QXP_I2C3_CLK:
|
||||||
|
case IMX8QXP_I2C3_IPG_CLK:
|
||||||
resource = SC_R_I2C_3;
|
resource = SC_R_I2C_3;
|
||||||
pm_clk = SC_PM_CLK_PER;
|
pm_clk = SC_PM_CLK_PER;
|
||||||
break;
|
break;
|
||||||
@ -234,18 +242,22 @@ int __imx8_clk_enable(struct clk *clk, bool enable)
|
|||||||
|
|
||||||
switch (clk->id) {
|
switch (clk->id) {
|
||||||
case IMX8QXP_I2C0_CLK:
|
case IMX8QXP_I2C0_CLK:
|
||||||
|
case IMX8QXP_I2C0_IPG_CLK:
|
||||||
resource = SC_R_I2C_0;
|
resource = SC_R_I2C_0;
|
||||||
pm_clk = SC_PM_CLK_PER;
|
pm_clk = SC_PM_CLK_PER;
|
||||||
break;
|
break;
|
||||||
case IMX8QXP_I2C1_CLK:
|
case IMX8QXP_I2C1_CLK:
|
||||||
|
case IMX8QXP_I2C1_IPG_CLK:
|
||||||
resource = SC_R_I2C_1;
|
resource = SC_R_I2C_1;
|
||||||
pm_clk = SC_PM_CLK_PER;
|
pm_clk = SC_PM_CLK_PER;
|
||||||
break;
|
break;
|
||||||
case IMX8QXP_I2C2_CLK:
|
case IMX8QXP_I2C2_CLK:
|
||||||
|
case IMX8QXP_I2C2_IPG_CLK:
|
||||||
resource = SC_R_I2C_2;
|
resource = SC_R_I2C_2;
|
||||||
pm_clk = SC_PM_CLK_PER;
|
pm_clk = SC_PM_CLK_PER;
|
||||||
break;
|
break;
|
||||||
case IMX8QXP_I2C3_CLK:
|
case IMX8QXP_I2C3_CLK:
|
||||||
|
case IMX8QXP_I2C3_IPG_CLK:
|
||||||
resource = SC_R_I2C_3;
|
resource = SC_R_I2C_3;
|
||||||
pm_clk = SC_PM_CLK_PER;
|
pm_clk = SC_PM_CLK_PER;
|
||||||
break;
|
break;
|
||||||
|
292
drivers/clk/imx/clk-imxrt1050.c
Normal file
292
drivers/clk/imx/clk-imxrt1050.c
Normal file
@ -0,0 +1,292 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright(C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <clk.h>
|
||||||
|
#include <clk-uclass.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <asm/arch/clock.h>
|
||||||
|
#include <asm/arch/imx-regs.h>
|
||||||
|
#include <dt-bindings/clock/imxrt1050-clock.h>
|
||||||
|
|
||||||
|
#include "clk.h"
|
||||||
|
|
||||||
|
static ulong imxrt1050_clk_get_rate(struct clk *clk)
|
||||||
|
{
|
||||||
|
struct clk *c;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
debug("%s(#%lu)\n", __func__, clk->id);
|
||||||
|
|
||||||
|
ret = clk_get_by_id(clk->id, &c);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
return clk_get_rate(c);
|
||||||
|
}
|
||||||
|
|
||||||
|
static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate)
|
||||||
|
{
|
||||||
|
struct clk *c;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
|
||||||
|
|
||||||
|
ret = clk_get_by_id(clk->id, &c);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
return clk_set_rate(c, rate);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int __imxrt1050_clk_enable(struct clk *clk, bool enable)
|
||||||
|
{
|
||||||
|
struct clk *c;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
|
||||||
|
|
||||||
|
ret = clk_get_by_id(clk->id, &c);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
if (enable)
|
||||||
|
ret = clk_enable(c);
|
||||||
|
else
|
||||||
|
ret = clk_disable(c);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int imxrt1050_clk_disable(struct clk *clk)
|
||||||
|
{
|
||||||
|
return __imxrt1050_clk_enable(clk, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int imxrt1050_clk_enable(struct clk *clk)
|
||||||
|
{
|
||||||
|
return __imxrt1050_clk_enable(clk, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct clk_ops imxrt1050_clk_ops = {
|
||||||
|
.set_rate = imxrt1050_clk_set_rate,
|
||||||
|
.get_rate = imxrt1050_clk_get_rate,
|
||||||
|
.enable = imxrt1050_clk_enable,
|
||||||
|
.disable = imxrt1050_clk_disable,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const pll_ref_sels[] = {"osc", "dummy", };
|
||||||
|
static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", };
|
||||||
|
static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", };
|
||||||
|
static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", };
|
||||||
|
static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", };
|
||||||
|
|
||||||
|
static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", };
|
||||||
|
static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
|
||||||
|
static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
|
||||||
|
static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
|
||||||
|
static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
|
||||||
|
static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
|
||||||
|
static const char *const lcdif_sels[] = { "pll2_sys", "pll3_pfd3_454_74m", "pll5_video:", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_664_62m"};
|
||||||
|
|
||||||
|
static int imxrt1050_clk_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
void *base;
|
||||||
|
|
||||||
|
/* Anatop clocks */
|
||||||
|
base = (void *)ANATOP_BASE_ADDR;
|
||||||
|
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
|
||||||
|
imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
|
||||||
|
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL2_REF_SEL,
|
||||||
|
imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2,
|
||||||
|
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL3_REF_SEL,
|
||||||
|
imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14, 2,
|
||||||
|
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL5_REF_SEL,
|
||||||
|
imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2,
|
||||||
|
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
|
||||||
|
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL1_ARM,
|
||||||
|
imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
|
||||||
|
base + 0x0, 0x7f));
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL2_SYS,
|
||||||
|
imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel",
|
||||||
|
base + 0x30, 0x1));
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,
|
||||||
|
imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
|
||||||
|
"pll3_usb_otg_ref_sel",
|
||||||
|
base + 0x10, 0x1));
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL5_VIDEO,
|
||||||
|
imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel",
|
||||||
|
base + 0xa0, 0x7f));
|
||||||
|
|
||||||
|
/* PLL bypass out */
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL1_BYPASS,
|
||||||
|
imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1,
|
||||||
|
pll1_bypass_sels,
|
||||||
|
ARRAY_SIZE(pll1_bypass_sels),
|
||||||
|
CLK_SET_RATE_PARENT));
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL2_BYPASS,
|
||||||
|
imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
|
||||||
|
pll2_bypass_sels,
|
||||||
|
ARRAY_SIZE(pll2_bypass_sels),
|
||||||
|
CLK_SET_RATE_PARENT));
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL3_BYPASS,
|
||||||
|
imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
|
||||||
|
pll3_bypass_sels,
|
||||||
|
ARRAY_SIZE(pll3_bypass_sels),
|
||||||
|
CLK_SET_RATE_PARENT));
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL5_BYPASS,
|
||||||
|
imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1,
|
||||||
|
pll5_bypass_sels,
|
||||||
|
ARRAY_SIZE(pll5_bypass_sels),
|
||||||
|
CLK_SET_RATE_PARENT));
|
||||||
|
|
||||||
|
clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL,
|
||||||
|
imx_clk_divider("video_post_div_sel", "pll5_video",
|
||||||
|
base + 0xa0, 19, 2));
|
||||||
|
clk_dm(IMXRT1050_CLK_VIDEO_DIV,
|
||||||
|
imx_clk_divider("video_div", "video_post_div_sel",
|
||||||
|
base + 0x170, 30, 2));
|
||||||
|
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL3_80M,
|
||||||
|
imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
|
||||||
|
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M,
|
||||||
|
imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL2_PFD1_594M,
|
||||||
|
imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1));
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL2_PFD2_396M,
|
||||||
|
imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2));
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL3_PFD1_664_62M,
|
||||||
|
imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0,
|
||||||
|
1));
|
||||||
|
clk_dm(IMXRT1050_CLK_PLL3_PFD3_454_74M,
|
||||||
|
imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0,
|
||||||
|
3));
|
||||||
|
|
||||||
|
/* CCM clocks */
|
||||||
|
base = dev_read_addr_ptr(dev);
|
||||||
|
if (base == (void *)FDT_ADDR_T_NONE)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
clk_dm(IMXRT1050_CLK_ARM_PODF,
|
||||||
|
imx_clk_divider("arm_podf", "pll1_arm",
|
||||||
|
base + 0x10, 0, 3));
|
||||||
|
|
||||||
|
clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL,
|
||||||
|
imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
|
||||||
|
pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
|
||||||
|
clk_dm(IMXRT1050_CLK_PERIPH_SEL,
|
||||||
|
imx_clk_mux("periph_sel", base + 0x14, 25, 1,
|
||||||
|
periph_sels, ARRAY_SIZE(periph_sels)));
|
||||||
|
clk_dm(IMXRT1050_CLK_USDHC1_SEL,
|
||||||
|
imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
|
||||||
|
usdhc_sels, ARRAY_SIZE(usdhc_sels)));
|
||||||
|
clk_dm(IMXRT1050_CLK_USDHC2_SEL,
|
||||||
|
imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
|
||||||
|
usdhc_sels, ARRAY_SIZE(usdhc_sels)));
|
||||||
|
clk_dm(IMXRT1050_CLK_LPUART_SEL,
|
||||||
|
imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
|
||||||
|
lpuart_sels, ARRAY_SIZE(lpuart_sels)));
|
||||||
|
clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL,
|
||||||
|
imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
|
||||||
|
semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
|
||||||
|
clk_dm(IMXRT1050_CLK_SEMC_SEL,
|
||||||
|
imx_clk_mux("semc_sel", base + 0x14, 6, 1,
|
||||||
|
semc_sels, ARRAY_SIZE(semc_sels)));
|
||||||
|
clk_dm(IMXRT1050_CLK_LCDIF_SEL,
|
||||||
|
imx_clk_mux("lcdif_sel", base + 0x38, 15, 3,
|
||||||
|
lcdif_sels, ARRAY_SIZE(lcdif_sels)));
|
||||||
|
|
||||||
|
clk_dm(IMXRT1050_CLK_AHB_PODF,
|
||||||
|
imx_clk_divider("ahb_podf", "periph_sel",
|
||||||
|
base + 0x14, 10, 3));
|
||||||
|
clk_dm(IMXRT1050_CLK_USDHC1_PODF,
|
||||||
|
imx_clk_divider("usdhc1_podf", "usdhc1_sel",
|
||||||
|
base + 0x24, 11, 3));
|
||||||
|
clk_dm(IMXRT1050_CLK_USDHC2_PODF,
|
||||||
|
imx_clk_divider("usdhc2_podf", "usdhc2_sel",
|
||||||
|
base + 0x24, 16, 3));
|
||||||
|
clk_dm(IMXRT1050_CLK_LPUART_PODF,
|
||||||
|
imx_clk_divider("lpuart_podf", "lpuart_sel",
|
||||||
|
base + 0x24, 0, 6));
|
||||||
|
clk_dm(IMXRT1050_CLK_SEMC_PODF,
|
||||||
|
imx_clk_divider("semc_podf", "semc_sel",
|
||||||
|
base + 0x14, 16, 3));
|
||||||
|
clk_dm(IMXRT1050_CLK_LCDIF_PRED,
|
||||||
|
imx_clk_divider("lcdif_pred", "lcdif_sel",
|
||||||
|
base + 0x38, 12, 3));
|
||||||
|
clk_dm(IMXRT1050_CLK_LCDIF_PODF,
|
||||||
|
imx_clk_divider("lcdif_podf", "lcdif_pred",
|
||||||
|
base + 0x18, 23, 3));
|
||||||
|
|
||||||
|
clk_dm(IMXRT1050_CLK_USDHC1,
|
||||||
|
imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
|
||||||
|
clk_dm(IMXRT1050_CLK_USDHC2,
|
||||||
|
imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
|
||||||
|
clk_dm(IMXRT1050_CLK_LPUART1,
|
||||||
|
imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
|
||||||
|
clk_dm(IMXRT1050_CLK_SEMC,
|
||||||
|
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
|
||||||
|
clk_dm(IMXRT1050_CLK_LCDIF,
|
||||||
|
imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
|
||||||
|
|
||||||
|
#ifdef CONFIG_SPL_BUILD
|
||||||
|
struct clk *clk, *clk1;
|
||||||
|
|
||||||
|
/* bypass pll1 before setting its rate */
|
||||||
|
clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk);
|
||||||
|
clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
|
||||||
|
clk_set_parent(clk1, clk);
|
||||||
|
|
||||||
|
clk_get_by_id(IMXRT1050_CLK_PLL1_ARM, &clk);
|
||||||
|
clk_enable(clk);
|
||||||
|
clk_set_rate(clk, 1056000000UL);
|
||||||
|
|
||||||
|
clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
|
||||||
|
clk_set_parent(clk1, clk);
|
||||||
|
|
||||||
|
clk_get_by_id(IMXRT1050_CLK_SEMC_SEL, &clk1);
|
||||||
|
clk_get_by_id(IMXRT1050_CLK_SEMC_ALT_SEL, &clk);
|
||||||
|
clk_set_parent(clk1, clk);
|
||||||
|
|
||||||
|
clk_get_by_id(IMXRT1050_CLK_PLL2_SYS, &clk);
|
||||||
|
clk_enable(clk);
|
||||||
|
clk_set_rate(clk, 528000000UL);
|
||||||
|
|
||||||
|
clk_get_by_id(IMXRT1050_CLK_PLL2_BYPASS, &clk1);
|
||||||
|
clk_set_parent(clk1, clk);
|
||||||
|
|
||||||
|
/* Configure PLL3_USB_OTG to 480MHz */
|
||||||
|
clk_get_by_id(IMXRT1050_CLK_PLL3_USB_OTG, &clk);
|
||||||
|
clk_enable(clk);
|
||||||
|
clk_set_rate(clk, 480000000UL);
|
||||||
|
|
||||||
|
clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1);
|
||||||
|
clk_set_parent(clk1, clk);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct udevice_id imxrt1050_clk_ids[] = {
|
||||||
|
{ .compatible = "fsl,imxrt1050-ccm" },
|
||||||
|
{ },
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(imxrt1050_clk) = {
|
||||||
|
.name = "clk_imxrt1050",
|
||||||
|
.id = UCLASS_CLK,
|
||||||
|
.of_match = imxrt1050_clk_ids,
|
||||||
|
.ops = &imxrt1050_clk_ops,
|
||||||
|
.probe = imxrt1050_clk_probe,
|
||||||
|
.flags = DM_FLAG_PRE_RELOC,
|
||||||
|
};
|
@ -52,8 +52,30 @@ static unsigned long clk_pfd_recalc_rate(struct clk *clk)
|
|||||||
return tmp;
|
return tmp;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static unsigned long clk_pfd_set_rate(struct clk *clk, unsigned long rate)
|
||||||
|
{
|
||||||
|
struct clk_pfd *pfd = to_clk_pfd(clk);
|
||||||
|
unsigned long parent_rate = clk_get_parent_rate(clk);
|
||||||
|
u64 tmp = parent_rate;
|
||||||
|
u8 frac;
|
||||||
|
|
||||||
|
tmp = tmp * 18 + rate / 2;
|
||||||
|
do_div(tmp, rate);
|
||||||
|
frac = tmp;
|
||||||
|
if (frac < 12)
|
||||||
|
frac = 12;
|
||||||
|
else if (frac > 35)
|
||||||
|
frac = 35;
|
||||||
|
|
||||||
|
writel(0x3f << (pfd->idx * 8), pfd->reg + CLR);
|
||||||
|
writel(frac << (pfd->idx * 8), pfd->reg + SET);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static const struct clk_ops clk_pfd_ops = {
|
static const struct clk_ops clk_pfd_ops = {
|
||||||
.get_rate = clk_pfd_recalc_rate,
|
.get_rate = clk_pfd_recalc_rate,
|
||||||
|
.set_rate = clk_pfd_set_rate,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct clk *imx_clk_pfd(const char *name, const char *parent_name,
|
struct clk *imx_clk_pfd(const char *name, const char *parent_name,
|
||||||
|
@ -6,6 +6,7 @@
|
|||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
|
#include <div64.h>
|
||||||
#include <malloc.h>
|
#include <malloc.h>
|
||||||
#include <clk-uclass.h>
|
#include <clk-uclass.h>
|
||||||
#include <dm/device.h>
|
#include <dm/device.h>
|
||||||
@ -13,18 +14,29 @@
|
|||||||
#include <clk.h>
|
#include <clk.h>
|
||||||
#include "clk.h"
|
#include "clk.h"
|
||||||
|
|
||||||
#define UBOOT_DM_CLK_IMX_PLLV3 "imx_clk_pllv3"
|
#define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic"
|
||||||
|
#define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys"
|
||||||
|
#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
|
||||||
|
#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
|
||||||
|
|
||||||
|
#define PLL_NUM_OFFSET 0x10
|
||||||
|
#define PLL_DENOM_OFFSET 0x20
|
||||||
|
|
||||||
|
#define BM_PLL_POWER (0x1 << 12)
|
||||||
|
#define BM_PLL_LOCK (0x1 << 31)
|
||||||
|
|
||||||
struct clk_pllv3 {
|
struct clk_pllv3 {
|
||||||
struct clk clk;
|
struct clk clk;
|
||||||
void __iomem *base;
|
void __iomem *base;
|
||||||
|
u32 power_bit;
|
||||||
|
bool powerup_set;
|
||||||
u32 div_mask;
|
u32 div_mask;
|
||||||
u32 div_shift;
|
u32 div_shift;
|
||||||
};
|
};
|
||||||
|
|
||||||
#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
|
#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
|
||||||
|
|
||||||
static ulong clk_pllv3_get_rate(struct clk *clk)
|
static ulong clk_pllv3_generic_get_rate(struct clk *clk)
|
||||||
{
|
{
|
||||||
struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
|
struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
|
||||||
unsigned long parent_rate = clk_get_parent_rate(clk);
|
unsigned long parent_rate = clk_get_parent_rate(clk);
|
||||||
@ -34,8 +46,165 @@ static ulong clk_pllv3_get_rate(struct clk *clk)
|
|||||||
return (div == 1) ? parent_rate * 22 : parent_rate * 20;
|
return (div == 1) ? parent_rate * 22 : parent_rate * 20;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static ulong clk_pllv3_generic_set_rate(struct clk *clk, ulong rate)
|
||||||
|
{
|
||||||
|
struct clk_pllv3 *pll = to_clk_pllv3(clk);
|
||||||
|
unsigned long parent_rate = clk_get_parent_rate(clk);
|
||||||
|
u32 val, div;
|
||||||
|
|
||||||
|
if (rate == parent_rate * 22)
|
||||||
|
div = 1;
|
||||||
|
else if (rate == parent_rate * 20)
|
||||||
|
div = 0;
|
||||||
|
else
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
val = readl(pll->base);
|
||||||
|
val &= ~(pll->div_mask << pll->div_shift);
|
||||||
|
val |= (div << pll->div_shift);
|
||||||
|
writel(val, pll->base);
|
||||||
|
|
||||||
|
/* Wait for PLL to lock */
|
||||||
|
while (!(readl(pll->base) & BM_PLL_LOCK))
|
||||||
|
;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int clk_pllv3_generic_enable(struct clk *clk)
|
||||||
|
{
|
||||||
|
struct clk_pllv3 *pll = to_clk_pllv3(clk);
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
val = readl(pll->base);
|
||||||
|
if (pll->powerup_set)
|
||||||
|
val |= pll->power_bit;
|
||||||
|
else
|
||||||
|
val &= ~pll->power_bit;
|
||||||
|
writel(val, pll->base);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int clk_pllv3_generic_disable(struct clk *clk)
|
||||||
|
{
|
||||||
|
struct clk_pllv3 *pll = to_clk_pllv3(clk);
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
val = readl(pll->base);
|
||||||
|
if (pll->powerup_set)
|
||||||
|
val &= ~pll->power_bit;
|
||||||
|
else
|
||||||
|
val |= pll->power_bit;
|
||||||
|
writel(val, pll->base);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static const struct clk_ops clk_pllv3_generic_ops = {
|
static const struct clk_ops clk_pllv3_generic_ops = {
|
||||||
.get_rate = clk_pllv3_get_rate,
|
.get_rate = clk_pllv3_generic_get_rate,
|
||||||
|
.enable = clk_pllv3_generic_enable,
|
||||||
|
.disable = clk_pllv3_generic_disable,
|
||||||
|
.set_rate = clk_pllv3_generic_set_rate,
|
||||||
|
};
|
||||||
|
|
||||||
|
static ulong clk_pllv3_sys_get_rate(struct clk *clk)
|
||||||
|
{
|
||||||
|
struct clk_pllv3 *pll = to_clk_pllv3(clk);
|
||||||
|
unsigned long parent_rate = clk_get_parent_rate(clk);
|
||||||
|
u32 div = readl(pll->base) & pll->div_mask;
|
||||||
|
|
||||||
|
return parent_rate * div / 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
|
||||||
|
{
|
||||||
|
struct clk_pllv3 *pll = to_clk_pllv3(clk);
|
||||||
|
unsigned long parent_rate = clk_get_parent_rate(clk);
|
||||||
|
unsigned long min_rate = parent_rate * 54 / 2;
|
||||||
|
unsigned long max_rate = parent_rate * 108 / 2;
|
||||||
|
u32 val, div;
|
||||||
|
|
||||||
|
if (rate < min_rate || rate > max_rate)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
div = rate * 2 / parent_rate;
|
||||||
|
val = readl(pll->base);
|
||||||
|
val &= ~pll->div_mask;
|
||||||
|
val |= div;
|
||||||
|
writel(val, pll->base);
|
||||||
|
|
||||||
|
/* Wait for PLL to lock */
|
||||||
|
while (!(readl(pll->base) & BM_PLL_LOCK))
|
||||||
|
;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct clk_ops clk_pllv3_sys_ops = {
|
||||||
|
.enable = clk_pllv3_generic_enable,
|
||||||
|
.disable = clk_pllv3_generic_disable,
|
||||||
|
.get_rate = clk_pllv3_sys_get_rate,
|
||||||
|
.set_rate = clk_pllv3_sys_set_rate,
|
||||||
|
};
|
||||||
|
|
||||||
|
static ulong clk_pllv3_av_get_rate(struct clk *clk)
|
||||||
|
{
|
||||||
|
struct clk_pllv3 *pll = to_clk_pllv3(clk);
|
||||||
|
unsigned long parent_rate = clk_get_parent_rate(clk);
|
||||||
|
u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
|
||||||
|
u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
|
||||||
|
u32 div = readl(pll->base) & pll->div_mask;
|
||||||
|
u64 temp64 = (u64)parent_rate;
|
||||||
|
|
||||||
|
temp64 *= mfn;
|
||||||
|
do_div(temp64, mfd);
|
||||||
|
|
||||||
|
return parent_rate * div + (unsigned long)temp64;
|
||||||
|
}
|
||||||
|
|
||||||
|
static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
|
||||||
|
{
|
||||||
|
struct clk_pllv3 *pll = to_clk_pllv3(clk);
|
||||||
|
unsigned long parent_rate = clk_get_parent_rate(clk);
|
||||||
|
unsigned long min_rate = parent_rate * 27;
|
||||||
|
unsigned long max_rate = parent_rate * 54;
|
||||||
|
u32 val, div;
|
||||||
|
u32 mfn, mfd = 1000000;
|
||||||
|
u32 max_mfd = 0x3FFFFFFF;
|
||||||
|
u64 temp64;
|
||||||
|
|
||||||
|
if (rate < min_rate || rate > max_rate)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (parent_rate <= max_mfd)
|
||||||
|
mfd = parent_rate;
|
||||||
|
|
||||||
|
div = rate / parent_rate;
|
||||||
|
temp64 = (u64)(rate - div * parent_rate);
|
||||||
|
temp64 *= mfd;
|
||||||
|
do_div(temp64, parent_rate);
|
||||||
|
mfn = temp64;
|
||||||
|
|
||||||
|
val = readl(pll->base);
|
||||||
|
val &= ~pll->div_mask;
|
||||||
|
val |= div;
|
||||||
|
writel(val, pll->base);
|
||||||
|
writel(mfn, pll->base + PLL_NUM_OFFSET);
|
||||||
|
writel(mfd, pll->base + PLL_DENOM_OFFSET);
|
||||||
|
|
||||||
|
/* Wait for PLL to lock */
|
||||||
|
while (!(readl(pll->base) & BM_PLL_LOCK))
|
||||||
|
;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct clk_ops clk_pllv3_av_ops = {
|
||||||
|
.enable = clk_pllv3_generic_enable,
|
||||||
|
.disable = clk_pllv3_generic_disable,
|
||||||
|
.get_rate = clk_pllv3_av_get_rate,
|
||||||
|
.set_rate = clk_pllv3_av_set_rate,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
|
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
|
||||||
@ -51,10 +220,28 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
|
|||||||
if (!pll)
|
if (!pll)
|
||||||
return ERR_PTR(-ENOMEM);
|
return ERR_PTR(-ENOMEM);
|
||||||
|
|
||||||
|
pll->power_bit = BM_PLL_POWER;
|
||||||
|
|
||||||
switch (type) {
|
switch (type) {
|
||||||
case IMX_PLLV3_GENERIC:
|
case IMX_PLLV3_GENERIC:
|
||||||
|
drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
|
||||||
|
pll->div_shift = 0;
|
||||||
|
pll->powerup_set = false;
|
||||||
|
break;
|
||||||
|
case IMX_PLLV3_SYS:
|
||||||
|
drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
|
||||||
|
pll->div_shift = 0;
|
||||||
|
pll->powerup_set = false;
|
||||||
|
break;
|
||||||
case IMX_PLLV3_USB:
|
case IMX_PLLV3_USB:
|
||||||
drv_name = UBOOT_DM_CLK_IMX_PLLV3;
|
drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
|
||||||
|
pll->div_shift = 1;
|
||||||
|
pll->powerup_set = true;
|
||||||
|
break;
|
||||||
|
case IMX_PLLV3_AV:
|
||||||
|
drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
|
||||||
|
pll->div_shift = 0;
|
||||||
|
pll->powerup_set = false;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
kfree(pll);
|
kfree(pll);
|
||||||
@ -75,8 +262,29 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
|
|||||||
}
|
}
|
||||||
|
|
||||||
U_BOOT_DRIVER(clk_pllv3_generic) = {
|
U_BOOT_DRIVER(clk_pllv3_generic) = {
|
||||||
.name = UBOOT_DM_CLK_IMX_PLLV3,
|
.name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC,
|
||||||
.id = UCLASS_CLK,
|
.id = UCLASS_CLK,
|
||||||
.ops = &clk_pllv3_generic_ops,
|
.ops = &clk_pllv3_generic_ops,
|
||||||
.flags = DM_FLAG_PRE_RELOC,
|
.flags = DM_FLAG_PRE_RELOC,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(clk_pllv3_sys) = {
|
||||||
|
.name = UBOOT_DM_CLK_IMX_PLLV3_SYS,
|
||||||
|
.id = UCLASS_CLK,
|
||||||
|
.ops = &clk_pllv3_sys_ops,
|
||||||
|
.flags = DM_FLAG_PRE_RELOC,
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(clk_pllv3_usb) = {
|
||||||
|
.name = UBOOT_DM_CLK_IMX_PLLV3_USB,
|
||||||
|
.id = UCLASS_CLK,
|
||||||
|
.ops = &clk_pllv3_generic_ops,
|
||||||
|
.flags = DM_FLAG_PRE_RELOC,
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(clk_pllv3_av) = {
|
||||||
|
.name = UBOOT_DM_CLK_IMX_PLLV3_AV,
|
||||||
|
.id = UCLASS_CLK,
|
||||||
|
.ops = &clk_pllv3_av_ops,
|
||||||
|
.flags = DM_FLAG_PRE_RELOC,
|
||||||
|
};
|
||||||
|
@ -41,14 +41,15 @@ static unsigned long gpio_ports[] = {
|
|||||||
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
|
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
|
||||||
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
|
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
|
||||||
defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
|
defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
|
||||||
defined(CONFIG_ARCH_IMX8)
|
defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
|
||||||
[3] = GPIO4_BASE_ADDR,
|
[3] = GPIO4_BASE_ADDR,
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
|
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
|
||||||
defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
|
defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
|
||||||
defined(CONFIG_ARCH_IMX8)
|
defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
|
||||||
[4] = GPIO5_BASE_ADDR,
|
[4] = GPIO5_BASE_ADDR,
|
||||||
#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M))
|
#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
|
||||||
|
defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT1050))
|
||||||
[5] = GPIO6_BASE_ADDR,
|
[5] = GPIO6_BASE_ADDR,
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
@ -732,7 +732,7 @@ config FSL_ESDHC_IMX
|
|||||||
|
|
||||||
config FSL_USDHC
|
config FSL_USDHC
|
||||||
bool "Freescale/NXP i.MX uSDHC controller support"
|
bool "Freescale/NXP i.MX uSDHC controller support"
|
||||||
depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || TARGET_S32V234EVB
|
depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT || TARGET_S32V234EVB
|
||||||
select FSL_ESDHC_IMX
|
select FSL_ESDHC_IMX
|
||||||
help
|
help
|
||||||
This enables the Ultra Secured Digital Host Controller enhancements
|
This enables the Ultra Secured Digital Host Controller enhancements
|
||||||
|
@ -78,7 +78,7 @@ struct fsl_esdhc {
|
|||||||
uint vendorspec;
|
uint vendorspec;
|
||||||
uint mmcboot;
|
uint mmcboot;
|
||||||
uint vendorspec2;
|
uint vendorspec2;
|
||||||
uint tuning_ctrl; /* on i.MX6/7/8 */
|
uint tuning_ctrl; /* on i.MX6/7/8/RT */
|
||||||
char reserved5[44];
|
char reserved5[44];
|
||||||
uint hostver; /* Host controller version register */
|
uint hostver; /* Host controller version register */
|
||||||
char reserved6[4]; /* reserved */
|
char reserved6[4]; /* reserved */
|
||||||
@ -115,6 +115,7 @@ struct esdhc_soc_data {
|
|||||||
* Following is used when Driver Model is enabled for MMC
|
* Following is used when Driver Model is enabled for MMC
|
||||||
* @dev: pointer for the device
|
* @dev: pointer for the device
|
||||||
* @non_removable: 0: removable; 1: non-removable
|
* @non_removable: 0: removable; 1: non-removable
|
||||||
|
* @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
|
||||||
* @wp_enable: 1: enable checking wp; 0: no check
|
* @wp_enable: 1: enable checking wp; 0: no check
|
||||||
* @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
|
* @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
|
||||||
* @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
|
* @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
|
||||||
@ -138,6 +139,7 @@ struct fsl_esdhc_priv {
|
|||||||
#endif
|
#endif
|
||||||
struct udevice *dev;
|
struct udevice *dev;
|
||||||
int non_removable;
|
int non_removable;
|
||||||
|
int broken_cd;
|
||||||
int wp_enable;
|
int wp_enable;
|
||||||
int vs18_enable;
|
int vs18_enable;
|
||||||
u32 flags;
|
u32 flags;
|
||||||
@ -1093,6 +1095,9 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
|
|||||||
#if CONFIG_IS_ENABLED(DM_MMC)
|
#if CONFIG_IS_ENABLED(DM_MMC)
|
||||||
if (priv->non_removable)
|
if (priv->non_removable)
|
||||||
return 1;
|
return 1;
|
||||||
|
|
||||||
|
if (priv->broken_cd)
|
||||||
|
return 1;
|
||||||
#if CONFIG_IS_ENABLED(DM_GPIO)
|
#if CONFIG_IS_ENABLED(DM_GPIO)
|
||||||
if (dm_gpio_is_valid(&priv->cd_gpio))
|
if (dm_gpio_is_valid(&priv->cd_gpio))
|
||||||
return dm_gpio_get_value(&priv->cd_gpio);
|
return dm_gpio_get_value(&priv->cd_gpio);
|
||||||
@ -1451,6 +1456,9 @@ static int fsl_esdhc_probe(struct udevice *dev)
|
|||||||
ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
|
ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
|
||||||
priv->strobe_dll_delay_target = val;
|
priv->strobe_dll_delay_target = val;
|
||||||
|
|
||||||
|
if (dev_read_bool(dev, "broken-cd"))
|
||||||
|
priv->broken_cd = 1;
|
||||||
|
|
||||||
if (dev_read_bool(dev, "non-removable")) {
|
if (dev_read_bool(dev, "non-removable")) {
|
||||||
priv->non_removable = 1;
|
priv->non_removable = 1;
|
||||||
} else {
|
} else {
|
||||||
@ -1515,27 +1523,27 @@ static int fsl_esdhc_probe(struct udevice *dev)
|
|||||||
|
|
||||||
init_clk_usdhc(dev->seq);
|
init_clk_usdhc(dev->seq);
|
||||||
|
|
||||||
if (CONFIG_IS_ENABLED(CLK)) {
|
#if CONFIG_IS_ENABLED(CLK)
|
||||||
/* Assigned clock already set clock */
|
/* Assigned clock already set clock */
|
||||||
ret = clk_get_by_name(dev, "per", &priv->per_clk);
|
ret = clk_get_by_name(dev, "per", &priv->per_clk);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
printf("Failed to get per_clk\n");
|
printf("Failed to get per_clk\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
|
||||||
ret = clk_enable(&priv->per_clk);
|
|
||||||
if (ret) {
|
|
||||||
printf("Failed to enable per_clk\n");
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
priv->sdhc_clk = clk_get_rate(&priv->per_clk);
|
|
||||||
} else {
|
|
||||||
priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
|
|
||||||
if (priv->sdhc_clk <= 0) {
|
|
||||||
dev_err(dev, "Unable to get clk for %s\n", dev->name);
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
ret = clk_enable(&priv->per_clk);
|
||||||
|
if (ret) {
|
||||||
|
printf("Failed to enable per_clk\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
priv->sdhc_clk = clk_get_rate(&priv->per_clk);
|
||||||
|
#else
|
||||||
|
priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
|
||||||
|
if (priv->sdhc_clk <= 0) {
|
||||||
|
dev_err(dev, "Unable to get clk for %s\n", dev->name);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
ret = fsl_esdhc_init(priv, plat);
|
ret = fsl_esdhc_init(priv, plat);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
@ -1652,6 +1660,7 @@ static const struct udevice_id fsl_esdhc_ids[] = {
|
|||||||
{ .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
|
{ .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
|
||||||
{ .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
|
{ .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
|
||||||
{ .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
|
{ .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
|
||||||
|
{ .compatible = "fsl,imxrt-usdhc", },
|
||||||
{ .compatible = "fsl,esdhc", },
|
{ .compatible = "fsl,esdhc", },
|
||||||
{ /* sentinel */ }
|
{ /* sentinel */ }
|
||||||
};
|
};
|
||||||
|
@ -99,6 +99,20 @@ config PINCTRL_MXS
|
|||||||
familiy, e.g. i.MX28. This feature depends on device tree
|
familiy, e.g. i.MX28. This feature depends on device tree
|
||||||
configuration.
|
configuration.
|
||||||
|
|
||||||
|
config PINCTRL_IMXRT
|
||||||
|
bool "IMXRT pinctrl driver"
|
||||||
|
depends on ARCH_IMXRT && PINCTRL_FULL
|
||||||
|
select DEVRES
|
||||||
|
select PINCTRL_IMX
|
||||||
|
help
|
||||||
|
Say Y here to enable the imxrt pinctrl driver
|
||||||
|
|
||||||
|
This provides a simple pinctrl driver for i.MXRT SoC familiy.
|
||||||
|
This feature depends on device tree configuration. This driver
|
||||||
|
is different from the linux one, this is a simple implementation,
|
||||||
|
only parses the 'fsl,pins' property and configure related
|
||||||
|
registers.
|
||||||
|
|
||||||
config PINCTRL_VYBRID
|
config PINCTRL_VYBRID
|
||||||
bool "Vybrid (vf610) pinctrl driver"
|
bool "Vybrid (vf610) pinctrl driver"
|
||||||
depends on ARCH_VF610 && PINCTRL_FULL
|
depends on ARCH_VF610 && PINCTRL_FULL
|
||||||
|
@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
|
|||||||
obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o
|
obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o
|
||||||
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
|
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
|
||||||
obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o
|
obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o
|
||||||
|
obj-$(CONFIG_PINCTRL_IMXRT) += pinctrl-imxrt.o
|
||||||
|
40
drivers/pinctrl/nxp/pinctrl-imxrt.c
Normal file
40
drivers/pinctrl/nxp/pinctrl-imxrt.c
Normal file
@ -0,0 +1,40 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <dm/pinctrl.h>
|
||||||
|
|
||||||
|
#include "pinctrl-imx.h"
|
||||||
|
|
||||||
|
static struct imx_pinctrl_soc_info imxrt_pinctrl_soc_info = {
|
||||||
|
.flags = ZERO_OFFSET_VALID,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int imxrt_pinctrl_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct imx_pinctrl_soc_info *info =
|
||||||
|
(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
|
||||||
|
|
||||||
|
return imx_pinctrl_probe(dev, info);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct udevice_id imxrt_pinctrl_match[] = {
|
||||||
|
{ .compatible = "fsl,imxrt-iomuxc",
|
||||||
|
.data = (ulong)&imxrt_pinctrl_soc_info },
|
||||||
|
{ /* sentinel */ }
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(imxrt_pinctrl) = {
|
||||||
|
.name = "imxrt-pinctrl",
|
||||||
|
.id = UCLASS_PINCTRL,
|
||||||
|
.of_match = of_match_ptr(imxrt_pinctrl_match),
|
||||||
|
.probe = imxrt_pinctrl_probe,
|
||||||
|
.remove = imx_pinctrl_remove,
|
||||||
|
.priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
|
||||||
|
.ops = &imx_pinctrl_ops,
|
||||||
|
.flags = DM_FLAG_PRE_RELOC,
|
||||||
|
};
|
@ -65,5 +65,13 @@ config K3_J721E_DDRSS
|
|||||||
Enabling this config adds support for the DDR memory controller
|
Enabling this config adds support for the DDR memory controller
|
||||||
on J721E family of SoCs.
|
on J721E family of SoCs.
|
||||||
|
|
||||||
|
config IMXRT_SDRAM
|
||||||
|
bool "Enable i.MXRT SDRAM support"
|
||||||
|
depends on RAM
|
||||||
|
help
|
||||||
|
i.MXRT family devices support smart external memory controller(SEMC)
|
||||||
|
to support external memories like sdram, psram & nand.
|
||||||
|
This driver is for the sdram memory interface with the SEMC.
|
||||||
|
|
||||||
source "drivers/ram/rockchip/Kconfig"
|
source "drivers/ram/rockchip/Kconfig"
|
||||||
source "drivers/ram/stm32mp1/Kconfig"
|
source "drivers/ram/stm32mp1/Kconfig"
|
||||||
|
@ -15,3 +15,5 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
|
|||||||
obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
|
obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
|
||||||
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
|
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
|
||||||
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
|
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
|
||||||
|
|
||||||
|
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
|
||||||
|
439
drivers/ram/imxrt_sdram.c
Normal file
439
drivers/ram/imxrt_sdram.c
Normal file
@ -0,0 +1,439 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <clk.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <ram.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
|
||||||
|
/* SDRAM Command Code */
|
||||||
|
#define SD_CC_ARD 0x0 /* Master Bus (AXI) command - Read */
|
||||||
|
#define SD_CC_AWR 0x1 /* Master Bus (AXI) command - Write */
|
||||||
|
#define SD_CC_IRD 0x8 /* IP command - Read */
|
||||||
|
#define SD_CC_IWR 0x9 /* IP command - Write */
|
||||||
|
#define SD_CC_IMS 0xA /* IP command - Set Mode Register */
|
||||||
|
#define SD_CC_IACT 0xB /* IP command - ACTIVE */
|
||||||
|
#define SD_CC_IAF 0xC /* IP command - Auto Refresh */
|
||||||
|
#define SD_CC_ISF 0xD /* IP Command - Self Refresh */
|
||||||
|
#define SD_CC_IPRE 0xE /* IP command - Precharge */
|
||||||
|
#define SD_CC_IPREA 0xF /* IP command - Precharge ALL */
|
||||||
|
|
||||||
|
#define SEMC_MCR_MDIS BIT(1)
|
||||||
|
#define SEMC_MCR_DQSMD BIT(2)
|
||||||
|
|
||||||
|
#define SEMC_INTR_IPCMDERR BIT(1)
|
||||||
|
#define SEMC_INTR_IPCMDDONE BIT(0)
|
||||||
|
|
||||||
|
#define SEMC_IPCMD_KEY 0xA55A0000
|
||||||
|
|
||||||
|
struct imxrt_semc_regs {
|
||||||
|
/* 0x0 */
|
||||||
|
u32 mcr;
|
||||||
|
u32 iocr;
|
||||||
|
u32 bmcr0;
|
||||||
|
u32 bmcr1;
|
||||||
|
u32 br[9];
|
||||||
|
|
||||||
|
/* 0x34 */
|
||||||
|
u32 res1;
|
||||||
|
u32 inten;
|
||||||
|
u32 intr;
|
||||||
|
/* 0x40 */
|
||||||
|
u32 sdramcr0;
|
||||||
|
u32 sdramcr1;
|
||||||
|
u32 sdramcr2;
|
||||||
|
u32 sdramcr3;
|
||||||
|
/* 0x50 */
|
||||||
|
u32 nandcr0;
|
||||||
|
u32 nandcr1;
|
||||||
|
u32 nandcr2;
|
||||||
|
u32 nandcr3;
|
||||||
|
/* 0x60 */
|
||||||
|
u32 norcr0;
|
||||||
|
u32 norcr1;
|
||||||
|
u32 norcr2;
|
||||||
|
u32 norcr3;
|
||||||
|
/* 0x70 */
|
||||||
|
u32 sramcr0;
|
||||||
|
u32 sramcr1;
|
||||||
|
u32 sramcr2;
|
||||||
|
u32 sramcr3;
|
||||||
|
/* 0x80 */
|
||||||
|
u32 dbicr0;
|
||||||
|
u32 dbicr1;
|
||||||
|
u32 res2[2];
|
||||||
|
/* 0x90 */
|
||||||
|
u32 ipcr0;
|
||||||
|
u32 ipcr1;
|
||||||
|
u32 ipcr2;
|
||||||
|
u32 ipcmd;
|
||||||
|
/* 0xA0 */
|
||||||
|
u32 iptxdat;
|
||||||
|
u32 res3[3];
|
||||||
|
/* 0xB0 */
|
||||||
|
u32 iprxdat;
|
||||||
|
u32 res4[3];
|
||||||
|
/* 0xC0 */
|
||||||
|
u32 sts[16];
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SEMC_IOCR_MUX_A8_SHIFT 0
|
||||||
|
#define SEMC_IOCR_MUX_CSX0_SHIFT 3
|
||||||
|
#define SEMC_IOCR_MUX_CSX1_SHIFT 6
|
||||||
|
#define SEMC_IOCR_MUX_CSX2_SHIFT 9
|
||||||
|
#define SEMC_IOCR_MUX_CSX3_SHIFT 12
|
||||||
|
#define SEMC_IOCR_MUX_RDY_SHIFT 15
|
||||||
|
|
||||||
|
struct imxrt_sdram_mux {
|
||||||
|
u8 a8;
|
||||||
|
u8 csx0;
|
||||||
|
u8 csx1;
|
||||||
|
u8 csx2;
|
||||||
|
u8 csx3;
|
||||||
|
u8 rdy;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SEMC_SDRAMCR0_PS_SHIFT 0
|
||||||
|
#define SEMC_SDRAMCR0_BL_SHIFT 4
|
||||||
|
#define SEMC_SDRAMCR0_COL_SHIFT 8
|
||||||
|
#define SEMC_SDRAMCR0_CL_SHIFT 10
|
||||||
|
|
||||||
|
struct imxrt_sdram_control {
|
||||||
|
u8 memory_width;
|
||||||
|
u8 burst_len;
|
||||||
|
u8 no_columns;
|
||||||
|
u8 cas_latency;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SEMC_SDRAMCR1_PRE2ACT_SHIFT 0
|
||||||
|
#define SEMC_SDRAMCR1_ACT2RW_SHIFT 4
|
||||||
|
#define SEMC_SDRAMCR1_RFRC_SHIFT 8
|
||||||
|
#define SEMC_SDRAMCR1_WRC_SHIFT 13
|
||||||
|
#define SEMC_SDRAMCR1_CKEOFF_SHIFT 16
|
||||||
|
#define SEMC_SDRAMCR1_ACT2PRE_SHIFT 20
|
||||||
|
|
||||||
|
#define SEMC_SDRAMCR2_SRRC_SHIFT 0
|
||||||
|
#define SEMC_SDRAMCR2_REF2REF_SHIFT 8
|
||||||
|
#define SEMC_SDRAMCR2_ACT2ACT_SHIFT 16
|
||||||
|
#define SEMC_SDRAMCR2_ITO_SHIFT 24
|
||||||
|
|
||||||
|
#define SEMC_SDRAMCR3_REN BIT(0)
|
||||||
|
#define SEMC_SDRAMCR3_REBL_SHIFT 1
|
||||||
|
#define SEMC_SDRAMCR3_PRESCALE_SHIFT 8
|
||||||
|
#define SEMC_SDRAMCR3_RT_SHIFT 16
|
||||||
|
#define SEMC_SDRAMCR3_UT_SHIFT 24
|
||||||
|
|
||||||
|
struct imxrt_sdram_timing {
|
||||||
|
u8 pre2act;
|
||||||
|
u8 act2rw;
|
||||||
|
u8 rfrc;
|
||||||
|
u8 wrc;
|
||||||
|
u8 ckeoff;
|
||||||
|
u8 act2pre;
|
||||||
|
|
||||||
|
u8 srrc;
|
||||||
|
u8 ref2ref;
|
||||||
|
u8 act2act;
|
||||||
|
u8 ito;
|
||||||
|
|
||||||
|
u8 rebl;
|
||||||
|
u8 prescale;
|
||||||
|
u8 rt;
|
||||||
|
u8 ut;
|
||||||
|
};
|
||||||
|
|
||||||
|
enum imxrt_semc_bank {
|
||||||
|
SDRAM_BANK1,
|
||||||
|
SDRAM_BANK2,
|
||||||
|
SDRAM_BANK3,
|
||||||
|
SDRAM_BANK4,
|
||||||
|
MAX_SDRAM_BANK,
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SEMC_BR_VLD_MASK 1
|
||||||
|
#define SEMC_BR_MS_SHIFT 1
|
||||||
|
|
||||||
|
struct bank_params {
|
||||||
|
enum imxrt_semc_bank target_bank;
|
||||||
|
u32 base_address;
|
||||||
|
u32 memory_size;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct imxrt_sdram_params {
|
||||||
|
struct imxrt_semc_regs *base;
|
||||||
|
|
||||||
|
struct imxrt_sdram_mux *sdram_mux;
|
||||||
|
struct imxrt_sdram_control *sdram_control;
|
||||||
|
struct imxrt_sdram_timing *sdram_timing;
|
||||||
|
|
||||||
|
struct bank_params bank_params[MAX_SDRAM_BANK];
|
||||||
|
u8 no_sdram_banks;
|
||||||
|
};
|
||||||
|
|
||||||
|
static int imxrt_sdram_wait_ipcmd_done(struct imxrt_semc_regs *regs)
|
||||||
|
{
|
||||||
|
do {
|
||||||
|
readl(®s->intr);
|
||||||
|
|
||||||
|
if (regs->intr & SEMC_INTR_IPCMDDONE)
|
||||||
|
return 0;
|
||||||
|
if (regs->intr & SEMC_INTR_IPCMDERR)
|
||||||
|
return -EIO;
|
||||||
|
|
||||||
|
mdelay(50);
|
||||||
|
} while (1);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int imxrt_sdram_ipcmd(struct imxrt_semc_regs *regs, u32 mem_addr,
|
||||||
|
u32 ipcmd, u32 wd, u32 *rd)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
if (ipcmd == SD_CC_IWR || ipcmd == SD_CC_IMS)
|
||||||
|
writel(wd, ®s->iptxdat);
|
||||||
|
|
||||||
|
/* set slave address for every command as specified on RM */
|
||||||
|
writel(mem_addr, ®s->ipcr0);
|
||||||
|
|
||||||
|
/* execute command */
|
||||||
|
writel(SEMC_IPCMD_KEY | ipcmd, ®s->ipcmd);
|
||||||
|
|
||||||
|
ret = imxrt_sdram_wait_ipcmd_done(regs);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
if (ipcmd == SD_CC_IRD) {
|
||||||
|
if (!rd)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
*rd = readl(®s->iprxdat);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int imxrt_sdram_init(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct imxrt_sdram_params *params = dev_get_platdata(dev);
|
||||||
|
struct imxrt_sdram_mux *mux = params->sdram_mux;
|
||||||
|
struct imxrt_sdram_control *ctrl = params->sdram_control;
|
||||||
|
struct imxrt_sdram_timing *time = params->sdram_timing;
|
||||||
|
struct imxrt_semc_regs *regs = params->base;
|
||||||
|
struct bank_params *bank_params;
|
||||||
|
u32 rd;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
/* enable the SEMC controller */
|
||||||
|
clrbits_le32(®s->mcr, SEMC_MCR_MDIS);
|
||||||
|
/* set DQS mode from DQS pad */
|
||||||
|
setbits_le32(®s->mcr, SEMC_MCR_DQSMD);
|
||||||
|
|
||||||
|
for (i = 0, bank_params = params->bank_params;
|
||||||
|
i < params->no_sdram_banks; bank_params++,
|
||||||
|
i++)
|
||||||
|
writel((bank_params->base_address & 0xfffff000)
|
||||||
|
| bank_params->memory_size << SEMC_BR_MS_SHIFT
|
||||||
|
| SEMC_BR_VLD_MASK,
|
||||||
|
®s->br[bank_params->target_bank]);
|
||||||
|
|
||||||
|
writel(mux->a8 << SEMC_IOCR_MUX_A8_SHIFT
|
||||||
|
| mux->csx0 << SEMC_IOCR_MUX_CSX0_SHIFT
|
||||||
|
| mux->csx1 << SEMC_IOCR_MUX_CSX1_SHIFT
|
||||||
|
| mux->csx2 << SEMC_IOCR_MUX_CSX2_SHIFT
|
||||||
|
| mux->csx3 << SEMC_IOCR_MUX_CSX3_SHIFT
|
||||||
|
| mux->rdy << SEMC_IOCR_MUX_RDY_SHIFT,
|
||||||
|
®s->iocr);
|
||||||
|
|
||||||
|
writel(ctrl->memory_width << SEMC_SDRAMCR0_PS_SHIFT
|
||||||
|
| ctrl->burst_len << SEMC_SDRAMCR0_BL_SHIFT
|
||||||
|
| ctrl->no_columns << SEMC_SDRAMCR0_COL_SHIFT
|
||||||
|
| ctrl->cas_latency << SEMC_SDRAMCR0_CL_SHIFT,
|
||||||
|
®s->sdramcr0);
|
||||||
|
|
||||||
|
writel(time->pre2act << SEMC_SDRAMCR1_PRE2ACT_SHIFT
|
||||||
|
| time->act2rw << SEMC_SDRAMCR1_ACT2RW_SHIFT
|
||||||
|
| time->rfrc << SEMC_SDRAMCR1_RFRC_SHIFT
|
||||||
|
| time->wrc << SEMC_SDRAMCR1_WRC_SHIFT
|
||||||
|
| time->ckeoff << SEMC_SDRAMCR1_CKEOFF_SHIFT
|
||||||
|
| time->act2pre << SEMC_SDRAMCR1_ACT2PRE_SHIFT,
|
||||||
|
®s->sdramcr1);
|
||||||
|
|
||||||
|
writel(time->srrc << SEMC_SDRAMCR2_SRRC_SHIFT
|
||||||
|
| time->ref2ref << SEMC_SDRAMCR2_REF2REF_SHIFT
|
||||||
|
| time->act2act << SEMC_SDRAMCR2_ACT2ACT_SHIFT
|
||||||
|
| time->ito << SEMC_SDRAMCR2_ITO_SHIFT,
|
||||||
|
®s->sdramcr2);
|
||||||
|
|
||||||
|
writel(time->rebl << SEMC_SDRAMCR3_REBL_SHIFT
|
||||||
|
| time->prescale << SEMC_SDRAMCR3_PRESCALE_SHIFT
|
||||||
|
| time->rt << SEMC_SDRAMCR3_RT_SHIFT
|
||||||
|
| time->ut << SEMC_SDRAMCR3_UT_SHIFT
|
||||||
|
| SEMC_SDRAMCR3_REN,
|
||||||
|
®s->sdramcr3);
|
||||||
|
|
||||||
|
writel(2, ®s->ipcr1);
|
||||||
|
|
||||||
|
for (i = 0, bank_params = params->bank_params;
|
||||||
|
i < params->no_sdram_banks; bank_params++,
|
||||||
|
i++) {
|
||||||
|
mdelay(250);
|
||||||
|
imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IPREA,
|
||||||
|
0, &rd);
|
||||||
|
imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
|
||||||
|
0, &rd);
|
||||||
|
imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
|
||||||
|
0, &rd);
|
||||||
|
imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IMS,
|
||||||
|
ctrl->burst_len | (ctrl->cas_latency << 4),
|
||||||
|
&rd);
|
||||||
|
mdelay(250);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int imxrt_semc_ofdata_to_platdata(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct imxrt_sdram_params *params = dev_get_platdata(dev);
|
||||||
|
ofnode bank_node;
|
||||||
|
u8 bank = 0;
|
||||||
|
|
||||||
|
params->sdram_mux =
|
||||||
|
(struct imxrt_sdram_mux *)
|
||||||
|
dev_read_u8_array_ptr(dev,
|
||||||
|
"fsl,sdram-mux",
|
||||||
|
sizeof(struct imxrt_sdram_mux));
|
||||||
|
if (!params->sdram_mux) {
|
||||||
|
pr_err("fsl,sdram-mux not found");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
params->sdram_control =
|
||||||
|
(struct imxrt_sdram_control *)
|
||||||
|
dev_read_u8_array_ptr(dev,
|
||||||
|
"fsl,sdram-control",
|
||||||
|
sizeof(struct imxrt_sdram_control));
|
||||||
|
if (!params->sdram_control) {
|
||||||
|
pr_err("fsl,sdram-control not found");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
params->sdram_timing =
|
||||||
|
(struct imxrt_sdram_timing *)
|
||||||
|
dev_read_u8_array_ptr(dev,
|
||||||
|
"fsl,sdram-timing",
|
||||||
|
sizeof(struct imxrt_sdram_timing));
|
||||||
|
if (!params->sdram_timing) {
|
||||||
|
pr_err("fsl,sdram-timing not found");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
dev_for_each_subnode(bank_node, dev) {
|
||||||
|
struct bank_params *bank_params;
|
||||||
|
char *bank_name;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
/* extract the bank index from DT */
|
||||||
|
bank_name = (char *)ofnode_get_name(bank_node);
|
||||||
|
strsep(&bank_name, "@");
|
||||||
|
if (!bank_name) {
|
||||||
|
pr_err("missing sdram bank index");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
bank_params = ¶ms->bank_params[bank];
|
||||||
|
strict_strtoul(bank_name, 10,
|
||||||
|
(unsigned long *)&bank_params->target_bank);
|
||||||
|
if (bank_params->target_bank >= MAX_SDRAM_BANK) {
|
||||||
|
pr_err("Found bank %d , but only bank 0,1,2,3 are supported",
|
||||||
|
bank_params->target_bank);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = ofnode_read_u32(bank_node,
|
||||||
|
"fsl,memory-size",
|
||||||
|
&bank_params->memory_size);
|
||||||
|
if (ret < 0) {
|
||||||
|
pr_err("fsl,memory-size not found");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = ofnode_read_u32(bank_node,
|
||||||
|
"fsl,base-address",
|
||||||
|
&bank_params->base_address);
|
||||||
|
if (ret < 0) {
|
||||||
|
pr_err("fsl,base-address not found");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
debug("Found bank %s %u\n", bank_name,
|
||||||
|
bank_params->target_bank);
|
||||||
|
bank++;
|
||||||
|
}
|
||||||
|
|
||||||
|
params->no_sdram_banks = bank;
|
||||||
|
debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int imxrt_semc_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct imxrt_sdram_params *params = dev_get_platdata(dev);
|
||||||
|
int ret;
|
||||||
|
fdt_addr_t addr;
|
||||||
|
|
||||||
|
addr = dev_read_addr(dev);
|
||||||
|
if (addr == FDT_ADDR_T_NONE)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
params->base = (struct imxrt_semc_regs *)addr;
|
||||||
|
|
||||||
|
#ifdef CONFIG_CLK
|
||||||
|
struct clk clk;
|
||||||
|
|
||||||
|
ret = clk_get_by_index(dev, 0, &clk);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = clk_enable(&clk);
|
||||||
|
|
||||||
|
if (ret) {
|
||||||
|
dev_err(dev, "failed to enable clock\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
ret = imxrt_sdram_init(dev);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int imxrt_semc_get_info(struct udevice *dev, struct ram_info *info)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct ram_ops imxrt_semc_ops = {
|
||||||
|
.get_info = imxrt_semc_get_info,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct udevice_id imxrt_semc_ids[] = {
|
||||||
|
{ .compatible = "fsl,imxrt-semc", .data = 0 },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(imxrt_semc) = {
|
||||||
|
.name = "imxrt_semc",
|
||||||
|
.id = UCLASS_RAM,
|
||||||
|
.of_match = imxrt_semc_ids,
|
||||||
|
.ops = &imxrt_semc_ops,
|
||||||
|
.ofdata_to_platdata = imxrt_semc_ofdata_to_platdata,
|
||||||
|
.probe = imxrt_semc_probe,
|
||||||
|
.platdata_auto_alloc_size = sizeof(struct imxrt_sdram_params),
|
||||||
|
};
|
@ -49,7 +49,7 @@
|
|||||||
#define FIFO_RXSIZE_MASK 0x7
|
#define FIFO_RXSIZE_MASK 0x7
|
||||||
#define FIFO_RXSIZE_OFF 0
|
#define FIFO_RXSIZE_OFF 0
|
||||||
#define FIFO_TXFE 0x80
|
#define FIFO_TXFE 0x80
|
||||||
#ifdef CONFIG_ARCH_IMX8
|
#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
|
||||||
#define FIFO_RXFE 0x08
|
#define FIFO_RXFE 0x08
|
||||||
#else
|
#else
|
||||||
#define FIFO_RXFE 0x40
|
#define FIFO_RXFE 0x40
|
||||||
@ -67,7 +67,8 @@ enum lpuart_devtype {
|
|||||||
DEV_VF610 = 1,
|
DEV_VF610 = 1,
|
||||||
DEV_LS1021A,
|
DEV_LS1021A,
|
||||||
DEV_MX7ULP,
|
DEV_MX7ULP,
|
||||||
DEV_IMX8
|
DEV_IMX8,
|
||||||
|
DEV_IMXRT,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct lpuart_serial_platdata {
|
struct lpuart_serial_platdata {
|
||||||
@ -409,7 +410,8 @@ static int _lpuart32_serial_init(struct udevice *dev)
|
|||||||
|
|
||||||
lpuart_write32(plat->flags, &base->match, 0);
|
lpuart_write32(plat->flags, &base->match, 0);
|
||||||
|
|
||||||
if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) {
|
if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
|
||||||
|
plat->devtype == DEV_IMXRT) {
|
||||||
_lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
|
_lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
|
||||||
} else {
|
} else {
|
||||||
/* provide data bits, parity, stop bit, etc */
|
/* provide data bits, parity, stop bit, etc */
|
||||||
@ -426,7 +428,8 @@ static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
|
|||||||
struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
|
struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
|
||||||
|
|
||||||
if (is_lpuart32(dev)) {
|
if (is_lpuart32(dev)) {
|
||||||
if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8)
|
if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
|
||||||
|
plat->devtype == DEV_IMXRT)
|
||||||
_lpuart32_serial_setbrg_7ulp(dev, baudrate);
|
_lpuart32_serial_setbrg_7ulp(dev, baudrate);
|
||||||
else
|
else
|
||||||
_lpuart32_serial_setbrg(dev, baudrate);
|
_lpuart32_serial_setbrg(dev, baudrate);
|
||||||
@ -483,6 +486,22 @@ static int lpuart_serial_pending(struct udevice *dev, bool input)
|
|||||||
|
|
||||||
static int lpuart_serial_probe(struct udevice *dev)
|
static int lpuart_serial_probe(struct udevice *dev)
|
||||||
{
|
{
|
||||||
|
#if CONFIG_IS_ENABLED(CLK)
|
||||||
|
struct clk per_clk;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = clk_get_by_name(dev, "per", &per_clk);
|
||||||
|
if (!ret) {
|
||||||
|
ret = clk_enable(&per_clk);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(dev, "Failed to get per clk: %d\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
dev_warn(dev, "Failed to get per clk: %d\n", ret);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
if (is_lpuart32(dev))
|
if (is_lpuart32(dev))
|
||||||
return _lpuart32_serial_init(dev);
|
return _lpuart32_serial_init(dev);
|
||||||
else
|
else
|
||||||
@ -514,6 +533,8 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
|
|||||||
plat->devtype = DEV_VF610;
|
plat->devtype = DEV_VF610;
|
||||||
else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
|
else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
|
||||||
plat->devtype = DEV_IMX8;
|
plat->devtype = DEV_IMX8;
|
||||||
|
else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
|
||||||
|
plat->devtype = DEV_IMXRT;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
@ -533,6 +554,8 @@ static const struct udevice_id lpuart_serial_ids[] = {
|
|||||||
{ .compatible = "fsl,vf610-lpuart"},
|
{ .compatible = "fsl,vf610-lpuart"},
|
||||||
{ .compatible = "fsl,imx8qm-lpuart",
|
{ .compatible = "fsl,imx8qm-lpuart",
|
||||||
.data = LPUART_FLAG_REGMAP_32BIT_REG },
|
.data = LPUART_FLAG_REGMAP_32BIT_REG },
|
||||||
|
{ .compatible = "fsl,imxrt-lpuart",
|
||||||
|
.data = LPUART_FLAG_REGMAP_32BIT_REG },
|
||||||
{ }
|
{ }
|
||||||
};
|
};
|
||||||
|
|
||||||
|
185
include/configs/capricorn-common.h
Normal file
185
include/configs/capricorn-common.h
Normal file
@ -0,0 +1,185 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright 2017-2018 NXP
|
||||||
|
* Copyright 2019 Siemens AG
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __IMX8X_CAPRICORN_H
|
||||||
|
#define __IMX8X_CAPRICORN_H
|
||||||
|
|
||||||
|
#include <linux/sizes.h>
|
||||||
|
#include <asm/arch/imx-regs.h>
|
||||||
|
|
||||||
|
#include "siemens-env-common.h"
|
||||||
|
#include "siemens-ccp-common.h"
|
||||||
|
|
||||||
|
/* SPL config */
|
||||||
|
#ifdef CONFIG_SPL_BUILD
|
||||||
|
|
||||||
|
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
|
||||||
|
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
|
||||||
|
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
||||||
|
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
|
||||||
|
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
|
||||||
|
|
||||||
|
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
|
||||||
|
#define CONFIG_SPL_STACK 0x013E000
|
||||||
|
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
|
||||||
|
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
|
||||||
|
#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
|
||||||
|
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
|
||||||
|
#define CONFIG_MALLOC_F_ADDR 0x00120000
|
||||||
|
|
||||||
|
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
|
||||||
|
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
|
||||||
|
|
||||||
|
#endif /* CONFIG_SPL_BUILD */
|
||||||
|
|
||||||
|
#define CONFIG_FACTORYSET
|
||||||
|
|
||||||
|
#undef CONFIG_IDENT_STRING
|
||||||
|
#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
|
||||||
|
|
||||||
|
#define CONFIG_REMAKE_ELF
|
||||||
|
|
||||||
|
#define CONFIG_BOARD_EARLY_INIT_F
|
||||||
|
|
||||||
|
/* Commands */
|
||||||
|
#define CONFIG_CMD_READ
|
||||||
|
|
||||||
|
#undef CONFIG_CMD_EXPORTENV
|
||||||
|
#undef CONFIG_CMD_IMPORTENV
|
||||||
|
#undef CONFIG_CMD_IMLS
|
||||||
|
#undef CONFIG_CMD_CRC32
|
||||||
|
#undef CONFIG_BOOTM_NETBSD
|
||||||
|
|
||||||
|
/* ENET Config */
|
||||||
|
#define CONFIG_FEC_XCV_TYPE RMII
|
||||||
|
#define FEC_QUIRK_ENET_MAC
|
||||||
|
|
||||||
|
/* ENET1 connects to base board and MUX with ESAI */
|
||||||
|
#define CONFIG_FEC_ENET_DEV 1
|
||||||
|
#define CONFIG_FEC_MXC_PHYADDR 0x0
|
||||||
|
#define CONFIG_ETHPRIME "eth1"
|
||||||
|
|
||||||
|
/* I2C Configuration */
|
||||||
|
#ifndef CONFIG_SPL_BUILD
|
||||||
|
#define CONFIG_SYS_I2C_SPEED 400000
|
||||||
|
/* EEPROM */
|
||||||
|
#define EEPROM_I2C_BUS 0 /* I2C0 */
|
||||||
|
#define EEPROM_I2C_ADDR 0x50
|
||||||
|
/* PCA9552 */
|
||||||
|
#define PCA9552_1_I2C_BUS 1 /* I2C1 */
|
||||||
|
#define PCA9552_1_I2C_ADDR 0x60
|
||||||
|
#endif /* !CONFIG_SPL_BUILD */
|
||||||
|
|
||||||
|
/* AHAB */
|
||||||
|
#ifdef CONFIG_AHAB_BOOT
|
||||||
|
#define AHAB_ENV "sec_boot=yes\0"
|
||||||
|
#else
|
||||||
|
#define AHAB_ENV "sec_boot=no\0"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define MFG_ENV_SETTINGS_DEFAULT \
|
||||||
|
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
|
||||||
|
"rdinit=/linuxrc " \
|
||||||
|
"clk_ignore_unused "\
|
||||||
|
"\0" \
|
||||||
|
"kboot=booti\0"\
|
||||||
|
"bootcmd_mfg=run mfgtool_args;" \
|
||||||
|
"if iminfo ${initrd_addr}; then " \
|
||||||
|
"if test ${tee} = yes; then " \
|
||||||
|
"bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
|
||||||
|
"else " \
|
||||||
|
"booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
|
||||||
|
"fi; " \
|
||||||
|
"else " \
|
||||||
|
"echo \"Run fastboot ...\"; fastboot 0; " \
|
||||||
|
"fi;\0"
|
||||||
|
|
||||||
|
/* Boot M4 */
|
||||||
|
#define M4_BOOT_ENV \
|
||||||
|
"m4_0_image=m4_0.bin\0" \
|
||||||
|
"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
|
||||||
|
"${loadaddr} ${m4_0_image}\0" \
|
||||||
|
"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
|
||||||
|
|
||||||
|
#define CONFIG_MFG_ENV_SETTINGS \
|
||||||
|
MFG_ENV_SETTINGS_DEFAULT \
|
||||||
|
"initrd_addr=0x83100000\0" \
|
||||||
|
"initrd_high=0xffffffffffffffff\0" \
|
||||||
|
"emmc_dev=0\0"
|
||||||
|
|
||||||
|
/* Initial environment variables */
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
CONFIG_MFG_ENV_SETTINGS \
|
||||||
|
M4_BOOT_ENV \
|
||||||
|
AHAB_ENV \
|
||||||
|
ENV_COMMON \
|
||||||
|
"script=boot.scr\0" \
|
||||||
|
"image=Image\0" \
|
||||||
|
"panel=NULL\0" \
|
||||||
|
"console=ttyLP2\0" \
|
||||||
|
"fdt_addr=0x83000000\0" \
|
||||||
|
"fdt_high=0xffffffffffffffff\0" \
|
||||||
|
"cntr_addr=0x88000000\0" \
|
||||||
|
"cntr_file=os_cntr_signed.bin\0" \
|
||||||
|
"initrd_addr=0x83800000\0" \
|
||||||
|
"initrd_high=0xffffffffffffffff\0" \
|
||||||
|
"netdev=eth0\0" \
|
||||||
|
"nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
|
||||||
|
"hostname=capricorn\0" \
|
||||||
|
ENV_EMMC \
|
||||||
|
ENV_NET
|
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND \
|
||||||
|
"if usrbutton; then " \
|
||||||
|
"run flash_self_test; " \
|
||||||
|
"reset; " \
|
||||||
|
"fi;" \
|
||||||
|
"run flash_self;" \
|
||||||
|
"reset;"
|
||||||
|
|
||||||
|
/* Default location for tftp and bootm */
|
||||||
|
#define CONFIG_LOADADDR 0x80280000
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||||
|
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
|
||||||
|
|
||||||
|
#define CONFIG_BOOTCOUNT_LIMIT
|
||||||
|
#define CONFIG_BOOTCOUNT_ENV
|
||||||
|
|
||||||
|
/* Environment organisation */
|
||||||
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1, eMMC */
|
||||||
|
#define CONFIG_SYS_MMC_ENV_PART 2 /* 2nd boot partition */
|
||||||
|
|
||||||
|
/* On CCP board, USDHC1 is for eMMC */
|
||||||
|
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */
|
||||||
|
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||||
|
|
||||||
|
/* Size of malloc() pool */
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
|
||||||
|
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||||
|
#define PHYS_SDRAM_1 0x80000000
|
||||||
|
#define PHYS_SDRAM_2 0x880000000
|
||||||
|
/* DDR3 board total DDR is 1 GB */
|
||||||
|
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
|
||||||
|
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MEMTEST_START 0xA0000000
|
||||||
|
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
|
||||||
|
(PHYS_SDRAM_1_SIZE >> 2))
|
||||||
|
|
||||||
|
/* Console buffer and boot args */
|
||||||
|
#define CONFIG_SYS_CBSIZE 2048
|
||||||
|
#define CONFIG_SYS_MAXARGS 64
|
||||||
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||||
|
|
||||||
|
/* Generic Timer Definitions */
|
||||||
|
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
|
||||||
|
|
||||||
|
#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
|
||||||
|
#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
|
||||||
|
|
||||||
|
#endif /* __IMX8X_CAPRICORN_H */
|
19
include/configs/deneb.h
Normal file
19
include/configs/deneb.h
Normal file
@ -0,0 +1,19 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright 2019 Siemens AG
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DENEB_H
|
||||||
|
#define __DENEB_H
|
||||||
|
|
||||||
|
#include "capricorn-common.h"
|
||||||
|
|
||||||
|
#undef CONFIG_IDENT_STRING
|
||||||
|
#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "06")
|
||||||
|
|
||||||
|
/* DDR3 board total DDR is 2 GB */
|
||||||
|
#undef PHYS_SDRAM_1_SIZE
|
||||||
|
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
|
||||||
|
|
||||||
|
#endif /* __DENEB_H */
|
19
include/configs/giedi.h
Normal file
19
include/configs/giedi.h
Normal file
@ -0,0 +1,19 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright 2019 Siemens AG
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __GIEDI_H
|
||||||
|
#define __GIEDI_H
|
||||||
|
|
||||||
|
#include "capricorn-common.h"
|
||||||
|
|
||||||
|
#undef CONFIG_IDENT_STRING
|
||||||
|
#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
|
||||||
|
|
||||||
|
/* DDR3 board total DDR is 1 GB */
|
||||||
|
#undef PHYS_SDRAM_1_SIZE
|
||||||
|
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
|
||||||
|
|
||||||
|
#endif /* __GIEDI_H */
|
46
include/configs/imxrt1050-evk.h
Normal file
46
include/configs/imxrt1050-evk.h
Normal file
@ -0,0 +1,46 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __IMXRT1050_EVK_H
|
||||||
|
#define __IMXRT1050_EVK_H
|
||||||
|
|
||||||
|
#include <asm/arch/imx-regs.h>
|
||||||
|
|
||||||
|
#define CONFIG_SYS_INIT_SP_ADDR 0x20280000
|
||||||
|
|
||||||
|
#ifdef CONFIG_SUPPORT_SPL
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR 0x20209000
|
||||||
|
#else
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR 0x80000000
|
||||||
|
#define CONFIG_LOADADDR 0x80000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
|
||||||
|
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
|
||||||
|
|
||||||
|
#define PHYS_SDRAM 0x80000000
|
||||||
|
#define PHYS_SDRAM_SIZE (32 * 1024 * 1024)
|
||||||
|
|
||||||
|
#define DMAMEM_SZ_ALL (1 * 1024 * 1024)
|
||||||
|
#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \
|
||||||
|
DMAMEM_SZ_ALL)
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration of the external SDRAM memory
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
|
||||||
|
|
||||||
|
/* For SPL */
|
||||||
|
#ifdef CONFIG_SUPPORT_SPL
|
||||||
|
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
|
||||||
|
#define CONFIG_SYS_SPL_LEN 0x00008000
|
||||||
|
#define CONFIG_SYS_UBOOT_START 0x800023FD
|
||||||
|
#endif
|
||||||
|
/* For SPL ends */
|
||||||
|
|
||||||
|
#endif /* __IMXRT1050_EVK_H */
|
@ -29,17 +29,6 @@
|
|||||||
|
|
||||||
#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
|
#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
|
||||||
|
|
||||||
/* Network */
|
|
||||||
#define CONFIG_FEC_MXC
|
|
||||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
|
||||||
#define CONFIG_ETHPRIME "FEC"
|
|
||||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
|
||||||
|
|
||||||
#define CONFIG_PHY_ATHEROS
|
|
||||||
|
|
||||||
/* ENET1 */
|
|
||||||
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
|
|
||||||
|
|
||||||
/* MMC Config */
|
/* MMC Config */
|
||||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||||
|
|
||||||
|
19
include/configs/siemens-ccp-common.h
Normal file
19
include/configs/siemens-ccp-common.h
Normal file
@ -0,0 +1,19 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/* Be very careful updating CONFIG_IDENT_STRING
|
||||||
|
* This string will control the update flow whether an U-Boot should be
|
||||||
|
* updated or not. If the version of installed U-Boot (in flash) is smaller
|
||||||
|
* than the version to be installed (from update file), an update will
|
||||||
|
* be performed.
|
||||||
|
*
|
||||||
|
* General rules:
|
||||||
|
* 1. First 4 characters ' ##v' or IDENT_MAGIC represent kind of a magic number
|
||||||
|
* to identify the following strings after easily. Don't change them!
|
||||||
|
*
|
||||||
|
* 2. First 2 digits after 'v' or CCP_MAJOR are updated with U-Boot version
|
||||||
|
* change, e.g. from 2015.04 to 2018.03
|
||||||
|
*
|
||||||
|
* 3. Second 2 digits after '.' or CCP_MINOR are updated if we want to upgrade
|
||||||
|
* U-Boot within an U-Boot version.
|
||||||
|
*/
|
||||||
|
#define CCP_IDENT_MAGIC " ##v"
|
||||||
|
#define GENERATE_CCP_VERSION(MAJOR, MINOR) CCP_IDENT_MAGIC MAJOR "." MINOR
|
201
include/configs/siemens-env-common.h
Normal file
201
include/configs/siemens-env-common.h
Normal file
@ -0,0 +1,201 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
|
||||||
|
/* Common env settings */
|
||||||
|
|
||||||
|
/** set_bootargs()
|
||||||
|
* input:
|
||||||
|
* console: string, tty, etc.
|
||||||
|
* baudrate: string, tty baudrate
|
||||||
|
* testargs: string
|
||||||
|
* optargs: string
|
||||||
|
* output:
|
||||||
|
* bootargs: string, default boot string
|
||||||
|
*/
|
||||||
|
#define ENV_BOOTARGS_DEFAULT "set_bootargs=" \
|
||||||
|
"setenv bootargs " \
|
||||||
|
"console=${console} " \
|
||||||
|
"${testargs} " \
|
||||||
|
"${optargs}\0"
|
||||||
|
|
||||||
|
/** set_bootargs_net()
|
||||||
|
* input:
|
||||||
|
* kernel_name:
|
||||||
|
* dtb_name:
|
||||||
|
* project_dir:
|
||||||
|
* output:
|
||||||
|
*/
|
||||||
|
#define ENV_NET_FCT_NETARGS "set_bootargs_net=" \
|
||||||
|
"run set_bootargs;" \
|
||||||
|
"setenv bootfile ${project_dir}/boot/${kernel_name};" \
|
||||||
|
"setenv bootdtb ${project_dir}/boot/${dtb_name_nfs}.dtb;" \
|
||||||
|
"setenv rootpath /home/projects/${project_dir}/;" \
|
||||||
|
"setenv bootargs ${bootargs} " \
|
||||||
|
"root=/dev/nfs " \
|
||||||
|
"nfsroot=${serverip}:${rootpath},${nfsopts} " \
|
||||||
|
"ip=${ipaddr}:${serverip}:" \
|
||||||
|
"${gatewayip}:${netmask}:${hostname}:eth0:off\0"
|
||||||
|
|
||||||
|
/** net_nfs()
|
||||||
|
* input:
|
||||||
|
* output:
|
||||||
|
*/
|
||||||
|
#define ENV_NET_FCT_BOOT "net_nfs=" \
|
||||||
|
"echo Booting from network ...; " \
|
||||||
|
"run set_bootargs_net; " \
|
||||||
|
"tftpboot ${dtb_loadaddr} ${serverip}:${bootdtb};" \
|
||||||
|
"if test $? -eq 1;" \
|
||||||
|
"then " \
|
||||||
|
"echo Loading default.dtb!;" \
|
||||||
|
"tftpboot ${dtb_loadaddr} ${serverip}:${project_dir}/boot/${dtb_name_default}.dtb;" \
|
||||||
|
"fi;" \
|
||||||
|
"tftpboot ${kernel_loadaddr} ${serverip}:${bootfile};" \
|
||||||
|
"printenv bootargs;" \
|
||||||
|
"booti ${kernel_loadaddr} - ${dtb_loadaddr}\0"
|
||||||
|
|
||||||
|
/** check_update()
|
||||||
|
* input:
|
||||||
|
* upgrade_available: [0|1], if set to 1 check bootcount variables
|
||||||
|
* bootcount: int, bootcount
|
||||||
|
* bootlimit: int, limit cootcount
|
||||||
|
* toggle_partition(): - toggles active partition set
|
||||||
|
* output:
|
||||||
|
* upgrade_available: [0|1], set to 0 if bootcount > bootlimit
|
||||||
|
*/
|
||||||
|
#define ENV_FCT_CHECK_UPGRADE "check_upgrade="\
|
||||||
|
"if test ${upgrade_available} -eq 1; " \
|
||||||
|
"then " \
|
||||||
|
"echo upgrade_available is set; " \
|
||||||
|
"if test ${bootcount} -gt ${bootlimit}; " \
|
||||||
|
"then " \
|
||||||
|
"setenv upgrade_available 0;" \
|
||||||
|
"echo toggle partition;" \
|
||||||
|
"run toggle_partition;" \
|
||||||
|
"fi;" \
|
||||||
|
"fi;\0"
|
||||||
|
|
||||||
|
/** toggle_partition()
|
||||||
|
* input:
|
||||||
|
* partitionset_active: [A|B], selected partition set
|
||||||
|
* output:
|
||||||
|
* partitionset_active: [A|B], toggle
|
||||||
|
*/
|
||||||
|
#define ENV_FCT_TOGGLE_PARTITION "toggle_partition="\
|
||||||
|
"setenv ${partitionset_active} true;" \
|
||||||
|
"if test -n ${A}; " \
|
||||||
|
"then " \
|
||||||
|
"setenv partitionset_active B; " \
|
||||||
|
"env delete A; " \
|
||||||
|
"fi;" \
|
||||||
|
"if test -n ${B}; "\
|
||||||
|
"then " \
|
||||||
|
"setenv partitionset_active A; " \
|
||||||
|
"env delete B; " \
|
||||||
|
"fi;" \
|
||||||
|
"saveenv\0"
|
||||||
|
|
||||||
|
/** set_partition()
|
||||||
|
* input:
|
||||||
|
* partitionset_active: [A|B], selected partition set
|
||||||
|
* rootfs_name: string, mmc device file in kernel, e.g. /dev/mmcblk0
|
||||||
|
* output:
|
||||||
|
* mmc_active_vol: string, mmc partition device file in kernel, e.g. /dev/mmcblk0p2
|
||||||
|
* mmc_part_nr: int, partition number of mmc, e.g. /dev/mmcblk0p2 --> 2
|
||||||
|
*/
|
||||||
|
#define ENV_EMMC_FCT_SET_ACTIVE_PARTITION "set_partition=" \
|
||||||
|
"setenv ${partitionset_active} true;" \
|
||||||
|
"if test -n ${A}; " \
|
||||||
|
"then " \
|
||||||
|
"setenv mmc_part_nr 1;" \
|
||||||
|
"fi;" \
|
||||||
|
"if test -n ${B}; " \
|
||||||
|
"then " \
|
||||||
|
"setenv mmc_part_nr 2;" \
|
||||||
|
"fi;" \
|
||||||
|
"setenv mmc_active_vol ${rootfs_name}p${mmc_part_nr} \0"
|
||||||
|
|
||||||
|
/** set_bootargs_mmc()
|
||||||
|
* input:
|
||||||
|
* bootargs: string, default bootargs
|
||||||
|
* mmc_active_vol string, mmc partition device file in kernel, e.g. /dev/mmcblk0p2
|
||||||
|
* ip_method: string, [none|?]
|
||||||
|
* output:
|
||||||
|
* bootargs: string
|
||||||
|
*/
|
||||||
|
#define ENV_EMMC_FCT_SET_EMMC_BOOTARGS "set_bootargs_mmc=" \
|
||||||
|
"setenv bootargs ${bootargs} " \
|
||||||
|
"root=${mmc_active_vol} rw " \
|
||||||
|
"rootdelay=1 rootwait " \
|
||||||
|
"rootfstype=ext4 " \
|
||||||
|
"ip=${ip_method} \0"
|
||||||
|
|
||||||
|
/** mmc_load_bootfiles()
|
||||||
|
* input:
|
||||||
|
* mmc_part_nr:
|
||||||
|
* dtb_loadaddr:
|
||||||
|
* dtb_name:
|
||||||
|
* kernel_loadaddr:
|
||||||
|
* kernel_name:
|
||||||
|
*/
|
||||||
|
#define ENV_EMMC_FCT_LOADFROM_EMMC "mmc_load_bootfiles=" \
|
||||||
|
"echo Loading from eMMC ...;" \
|
||||||
|
"ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name}.dtb;" \
|
||||||
|
"if test $? -eq 1;" \
|
||||||
|
"then " \
|
||||||
|
"echo Loading default.dtb!;" \
|
||||||
|
"ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name_default}.dtb;" \
|
||||||
|
"fi;" \
|
||||||
|
"ext4load mmc 0:${mmc_part_nr} ${kernel_loadaddr} boot/${kernel_name};" \
|
||||||
|
"printenv bootargs;\0"
|
||||||
|
|
||||||
|
/** mmc_boot()
|
||||||
|
* input:
|
||||||
|
* mmc_part_nr:
|
||||||
|
* dtb_loadaddr:
|
||||||
|
* dtb_name:
|
||||||
|
* kernel_loadaddr:
|
||||||
|
* kernel_name:
|
||||||
|
*/
|
||||||
|
#define ENV_EMMC_FCT_EMMC_BOOT "mmc_boot=" \
|
||||||
|
"run set_bootargs;" \
|
||||||
|
"run check_upgrade; " \
|
||||||
|
"run set_partition;" \
|
||||||
|
"run set_bootargs_mmc;" \
|
||||||
|
"run mmc_load_bootfiles;" \
|
||||||
|
"echo Booting from eMMC ...; " \
|
||||||
|
"booti ${kernel_loadaddr} - ${dtb_loadaddr} \0"
|
||||||
|
|
||||||
|
#define ENV_EMMC_ALIASES "" \
|
||||||
|
"flash_self=run mmc_boot\0" \
|
||||||
|
"flash_self_test=setenv testargs test; " \
|
||||||
|
"run mmc_boot\0"
|
||||||
|
|
||||||
|
#define ENV_COMMON "" \
|
||||||
|
"project_dir=targetdir/rootfs\0" \
|
||||||
|
"serverip=192.168.251.2\0" \
|
||||||
|
"ipaddr=192.168.251.1\0" \
|
||||||
|
"dtb_name_nfs=default\0" \
|
||||||
|
"dtb_name_default=default\0" \
|
||||||
|
"kernel_name=Image\0" \
|
||||||
|
"partitionset_active=A\0" \
|
||||||
|
"dtb_loadaddr=0x83000000\0" \
|
||||||
|
"kernel_loadaddr=0x80280000\0" \
|
||||||
|
"ip_method=none\0" \
|
||||||
|
"rootfs_name=/dev/mmcblk0\0" \
|
||||||
|
"upgrade_available=0\0" \
|
||||||
|
"bootlimit=3\0" \
|
||||||
|
"altbootcmd=run bootcmd\0" \
|
||||||
|
"optargs=\0" \
|
||||||
|
|
||||||
|
/**********************************************************************/
|
||||||
|
|
||||||
|
#define ENV_EMMC ENV_EMMC_FCT_EMMC_BOOT \
|
||||||
|
ENV_EMMC_FCT_LOADFROM_EMMC \
|
||||||
|
ENV_EMMC_FCT_SET_EMMC_BOOTARGS \
|
||||||
|
ENV_EMMC_FCT_SET_ACTIVE_PARTITION \
|
||||||
|
ENV_FCT_CHECK_UPGRADE \
|
||||||
|
ENV_EMMC_ALIASES \
|
||||||
|
ENV_FCT_TOGGLE_PARTITION
|
||||||
|
|
||||||
|
#define ENV_NET ENV_NET_FCT_BOOT \
|
||||||
|
ENV_NET_FCT_NETARGS \
|
||||||
|
ENV_BOOTARGS_DEFAULT
|
65
include/dt-bindings/clock/imxrt1050-clock.h
Normal file
65
include/dt-bindings/clock/imxrt1050-clock.h
Normal file
@ -0,0 +1,65 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright(C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H
|
||||||
|
#define __DT_BINDINGS_CLOCK_IMXRT1050_H
|
||||||
|
|
||||||
|
#define IMXRT1050_CLK_DUMMY 0
|
||||||
|
#define IMXRT1050_CLK_CKIL 1
|
||||||
|
#define IMXRT1050_CLK_CKIH 2
|
||||||
|
#define IMXRT1050_CLK_OSC 3
|
||||||
|
#define IMXRT1050_CLK_PLL2_PFD0_352M 4
|
||||||
|
#define IMXRT1050_CLK_PLL2_PFD1_594M 5
|
||||||
|
#define IMXRT1050_CLK_PLL2_PFD2_396M 6
|
||||||
|
#define IMXRT1050_CLK_PLL3_PFD0_720M 7
|
||||||
|
#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8
|
||||||
|
#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9
|
||||||
|
#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10
|
||||||
|
#define IMXRT1050_CLK_PLL2_198M 11
|
||||||
|
#define IMXRT1050_CLK_PLL3_120M 12
|
||||||
|
#define IMXRT1050_CLK_PLL3_80M 13
|
||||||
|
#define IMXRT1050_CLK_PLL3_60M 14
|
||||||
|
#define IMXRT1050_CLK_PLL1_BYPASS 15
|
||||||
|
#define IMXRT1050_CLK_PLL2_BYPASS 16
|
||||||
|
#define IMXRT1050_CLK_PLL3_BYPASS 17
|
||||||
|
#define IMXRT1050_CLK_PLL5_BYPASS 19
|
||||||
|
#define IMXRT1050_CLK_PLL1_REF_SEL 20
|
||||||
|
#define IMXRT1050_CLK_PLL2_REF_SEL 21
|
||||||
|
#define IMXRT1050_CLK_PLL3_REF_SEL 22
|
||||||
|
#define IMXRT1050_CLK_PLL5_REF_SEL 23
|
||||||
|
#define IMXRT1050_CLK_PRE_PERIPH_SEL 24
|
||||||
|
#define IMXRT1050_CLK_PERIPH_SEL 25
|
||||||
|
#define IMXRT1050_CLK_SEMC_ALT_SEL 26
|
||||||
|
#define IMXRT1050_CLK_SEMC_SEL 27
|
||||||
|
#define IMXRT1050_CLK_USDHC1_SEL 28
|
||||||
|
#define IMXRT1050_CLK_USDHC2_SEL 29
|
||||||
|
#define IMXRT1050_CLK_LPUART_SEL 30
|
||||||
|
#define IMXRT1050_CLK_LCDIF_SEL 31
|
||||||
|
#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32
|
||||||
|
#define IMXRT1050_CLK_VIDEO_DIV 33
|
||||||
|
#define IMXRT1050_CLK_ARM_PODF 34
|
||||||
|
#define IMXRT1050_CLK_LPUART_PODF 35
|
||||||
|
#define IMXRT1050_CLK_USDHC1_PODF 36
|
||||||
|
#define IMXRT1050_CLK_USDHC2_PODF 37
|
||||||
|
#define IMXRT1050_CLK_SEMC_PODF 38
|
||||||
|
#define IMXRT1050_CLK_AHB_PODF 39
|
||||||
|
#define IMXRT1050_CLK_LCDIF_PRED 40
|
||||||
|
#define IMXRT1050_CLK_LCDIF_PODF 41
|
||||||
|
#define IMXRT1050_CLK_USDHC1 42
|
||||||
|
#define IMXRT1050_CLK_USDHC2 43
|
||||||
|
#define IMXRT1050_CLK_LPUART1 44
|
||||||
|
#define IMXRT1050_CLK_SEMC 45
|
||||||
|
#define IMXRT1050_CLK_LCDIF 46
|
||||||
|
#define IMXRT1050_CLK_PLL1_ARM 47
|
||||||
|
#define IMXRT1050_CLK_PLL2_SYS 48
|
||||||
|
#define IMXRT1050_CLK_PLL3_USB_OTG 49
|
||||||
|
#define IMXRT1050_CLK_PLL4_AUDIO 50
|
||||||
|
#define IMXRT1050_CLK_PLL5_VIDEO 51
|
||||||
|
#define IMXRT1050_CLK_PLL6_ENET 52
|
||||||
|
#define IMXRT1050_CLK_PLL7_USB_HOST 53
|
||||||
|
#define IMXRT1050_CLK_END 54
|
||||||
|
|
||||||
|
#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
|
100
include/dt-bindings/memory/imxrt-sdram.h
Normal file
100
include/dt-bindings/memory/imxrt-sdram.h
Normal file
@ -0,0 +1,100 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef DT_BINDINGS_IMXRT_SDRAM_H
|
||||||
|
#define DT_BINDINGS_IMXRT_SDRAM_H
|
||||||
|
|
||||||
|
#define MEM_SIZE_4K 0x00
|
||||||
|
#define MEM_SIZE_8K 0x01
|
||||||
|
#define MEM_SIZE_16K 0x02
|
||||||
|
#define MEM_SIZE_32K 0x03
|
||||||
|
#define MEM_SIZE_64K 0x04
|
||||||
|
#define MEM_SIZE_128K 0x05
|
||||||
|
#define MEM_SIZE_256K 0x06
|
||||||
|
#define MEM_SIZE_512K 0x07
|
||||||
|
#define MEM_SIZE_1M 0x08
|
||||||
|
#define MEM_SIZE_2M 0x09
|
||||||
|
#define MEM_SIZE_4M 0x0A
|
||||||
|
#define MEM_SIZE_8M 0x0B
|
||||||
|
#define MEM_SIZE_16M 0x0C
|
||||||
|
#define MEM_SIZE_32M 0x0D
|
||||||
|
#define MEM_SIZE_64M 0x0E
|
||||||
|
#define MEM_SIZE_128M 0x0F
|
||||||
|
#define MEM_SIZE_256M 0x10
|
||||||
|
#define MEM_SIZE_512M 0x11
|
||||||
|
#define MEM_SIZE_1G 0x12
|
||||||
|
#define MEM_SIZE_2G 0x13
|
||||||
|
#define MEM_SIZE_4G 0x14
|
||||||
|
|
||||||
|
#define MUX_A8_SDRAM_A8 0x0
|
||||||
|
#define MUX_A8_NAND_CE 0x1
|
||||||
|
#define MUX_A8_NOR_CE 0x2
|
||||||
|
#define MUX_A8_PSRAM_CE 0x3
|
||||||
|
#define MUX_A8_DBI_CSX 0x4
|
||||||
|
|
||||||
|
#define MUX_CSX0_NOR_PSRAM_A24 0x0
|
||||||
|
#define MUX_CSX0_SDRAM_CS1 0x1
|
||||||
|
#define MUX_CSX0_SDRAM_CS2 0x2
|
||||||
|
#define MUX_CSX0_SDRAM_CS3 0x3
|
||||||
|
#define MUX_CSX0_NAND_CE 0x4
|
||||||
|
#define MUX_CSX0_NOR_CE 0x5
|
||||||
|
#define MUX_CSX0_PSRAM_CE 0x6
|
||||||
|
#define MUX_CSX0_DBI_CSX 0x7
|
||||||
|
|
||||||
|
#define MUX_CSX1_NOR_PSRAM_A25 0x0
|
||||||
|
#define MUX_CSX1_SDRAM_CS1 0x1
|
||||||
|
#define MUX_CSX1_SDRAM_CS2 0x2
|
||||||
|
#define MUX_CSX1_SDRAM_CS3 0x3
|
||||||
|
#define MUX_CSX1_NAND_CE 0x4
|
||||||
|
#define MUX_CSX1_NOR_CE 0x5
|
||||||
|
#define MUX_CSX1_PSRAM_CE 0x6
|
||||||
|
#define MUX_CSX1_DBI_CSX 0x7
|
||||||
|
|
||||||
|
#define MUX_CSX2_NOR_PSRAM_A26 0x0
|
||||||
|
#define MUX_CSX2_SDRAM_CS1 0x1
|
||||||
|
#define MUX_CSX2_SDRAM_CS2 0x2
|
||||||
|
#define MUX_CSX2_SDRAM_CS3 0x3
|
||||||
|
#define MUX_CSX2_NAND_CE 0x4
|
||||||
|
#define MUX_CSX2_NOR_CE 0x5
|
||||||
|
#define MUX_CSX2_PSRAM_CE 0x6
|
||||||
|
#define MUX_CSX2_DBI_CSX 0x7
|
||||||
|
|
||||||
|
#define MUX_CSX3_NOR_PSRAM_A27 0x0
|
||||||
|
#define MUX_CSX3_SDRAM_CS1 0x1
|
||||||
|
#define MUX_CSX3_SDRAM_CS2 0x2
|
||||||
|
#define MUX_CSX3_SDRAM_CS3 0x3
|
||||||
|
#define MUX_CSX3_NAND_CE 0x4
|
||||||
|
#define MUX_CSX3_NOR_CE 0x5
|
||||||
|
#define MUX_CSX3_PSRAM_CE 0x6
|
||||||
|
#define MUX_CSX3_DBI_CSX 0x7
|
||||||
|
|
||||||
|
#define MUX_RDY_NAND_RDY_WAIT 0x0
|
||||||
|
#define MUX_RDY_SDRAM_CS1 0x1
|
||||||
|
#define MUX_RDY_SDRAM_CS2 0x2
|
||||||
|
#define MUX_RDY_SDRAM_CS3 0x3
|
||||||
|
#define MUX_RDY_NOR_CE 0x4
|
||||||
|
#define MUX_RDY_PSRAM_CE 0x5
|
||||||
|
#define MUX_RDY_DBI_CSX 0x6
|
||||||
|
#define MUX_RDY_NOR_PSRAM_A27 0x7
|
||||||
|
|
||||||
|
#define MEM_WIDTH_8BITS 0x0
|
||||||
|
#define MEM_WIDTH_16BITS 0x1
|
||||||
|
|
||||||
|
#define BL_1 0x0
|
||||||
|
#define BL_2 0x1
|
||||||
|
#define BL_4 0x2
|
||||||
|
#define BL_8 0x3
|
||||||
|
|
||||||
|
#define COL_12BITS 0x0
|
||||||
|
#define COL_11BITS 0x1
|
||||||
|
#define COL_10BITS 0x2
|
||||||
|
#define COL_9BITS 0x3
|
||||||
|
|
||||||
|
#define CL_1 0x0
|
||||||
|
#define CL_2 0x2
|
||||||
|
#define CL_3 0x3
|
||||||
|
|
||||||
|
#endif
|
993
include/dt-bindings/pinctrl/pins-imxrt1050.h
Normal file
993
include/dt-bindings/pinctrl/pins-imxrt1050.h
Normal file
@ -0,0 +1,993 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2019
|
||||||
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
|
||||||
|
#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
|
||||||
|
|
||||||
|
#define IMX_PAD_SION 0x40000000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The pin function ID is a tuple of
|
||||||
|
* <mux_reg conf_reg input_reg mux_mode input_val>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0
|
||||||
|
#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0
|
||||||
|
|
||||||
|
#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */
|
@ -4,7 +4,8 @@
|
|||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8)
|
#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \
|
||||||
|
defined(CONFIG_ARCH_IMXRT)
|
||||||
struct lpuart_fsl_reg32 {
|
struct lpuart_fsl_reg32 {
|
||||||
u32 verid;
|
u32 verid;
|
||||||
u32 param;
|
u32 param;
|
||||||
|
Loading…
Reference in New Issue
Block a user