mirror of
https://github.com/brain-hackers/u-boot-brain
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- Sync r8a774a1 DT files, tmio sdhi DMA fix
This commit is contained in:
commit
fad42d3afb
377
arch/arm/dts/hihope-common.dtsi
Normal file
377
arch/arm/dts/hihope-common.dtsi
Normal file
@ -0,0 +1,377 @@
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||||
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
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||||
* HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases {
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serial0 = &scif2;
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serial1 = &hscif0;
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};
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chosen {
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bootargs = "ignore_loglevel";
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stdout-path = "serial0:115200n8";
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};
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hdmi0-out {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi0_con: endpoint {
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remote-endpoint = <&rcar_dw_hdmi0_out>;
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};
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};
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};
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leds {
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compatible = "gpio-leds";
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led1 {
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gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
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};
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led2 {
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gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
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};
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led3 {
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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};
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led4 {
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gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>;
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};
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};
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reg_1p8v: regulator0 {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator1 {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sound_card: sound {
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compatible = "audio-graph-card";
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label = "rcar-sound";
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dais = <&rsnd_port>;
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};
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vbus0_usb2: regulator-vbus0-usb2 {
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compatible = "regulator-fixed";
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regulator-name = "USB20_VBUS0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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vccq_sdhi0: regulator-vccq-sdhi0 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI0 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1>, <1800000 0>;
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};
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x302_clk: x302-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <33000000>;
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};
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x304_clk: x304-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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&audio_clk_a {
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clock-frequency = <22579200>;
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};
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&du {
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status = "okay";
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};
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&ehci0 {
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status = "okay";
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};
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&ehci1 {
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status = "okay";
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};
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&extal_clk {
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clock-frequency = <16666666>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&gpio6 {
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usb1-reset {
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gpio-hog;
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gpios = <10 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "usb1-reset";
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};
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};
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&hdmi0 {
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status = "okay";
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ports {
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port@1 {
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reg = <1>;
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rcar_dw_hdmi0_out: endpoint {
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remote-endpoint = <&hdmi0_con>;
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};
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};
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port@2 {
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reg = <2>;
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dw_hdmi0_snd_in: endpoint {
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remote-endpoint = <&rsnd_endpoint>;
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};
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};
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};
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};
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&hscif0 {
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pinctrl-0 = <&hscif0_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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&hsusb {
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dr_mode = "otg";
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status = "okay";
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};
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&i2c4 {
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clock-frequency = <400000>;
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status = "okay";
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versaclock5: clock-generator@6a {
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compatible = "idt,5p49v5923";
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reg = <0x6a>;
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#clock-cells = <1>;
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clocks = <&x304_clk>;
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clock-names = "xin";
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};
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};
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&ohci0 {
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status = "okay";
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};
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&ohci1 {
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status = "okay";
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};
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&pcie_bus_clk {
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clock-frequency = <100000000>;
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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hscif0_pins: hscif0 {
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groups = "hscif0_data", "hscif0_ctrl";
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function = "hscif0";
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};
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scif2_pins: scif2 {
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groups = "scif2_data_a";
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function = "scif2";
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};
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scif_clk_pins: scif_clk {
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groups = "scif_clk_a";
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function = "scif_clk";
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};
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sdhi0_pins: sd0 {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <3300>;
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};
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sdhi0_pins_uhs: sd0_uhs {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <1800>;
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};
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sdhi2_pins: sd2 {
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groups = "sdhi2_data4", "sdhi2_ctrl";
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function = "sdhi2";
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power-source = <1800>;
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};
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sdhi3_pins: sd3 {
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groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
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function = "sdhi3";
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power-source = <1800>;
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};
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usb0_pins: usb0 {
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groups = "usb0";
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function = "usb0";
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};
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usb1_pins: usb1 {
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mux {
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groups = "usb1";
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function = "usb1";
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};
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ovc {
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pins = "GP_6_27";
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bias-pull-up;
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};
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};
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usb30_pins: usb30 {
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groups = "usb30";
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function = "usb30";
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};
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};
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&rwdt {
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timeout-sec = <60>;
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status = "okay";
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};
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&scif2 {
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pinctrl-0 = <&scif2_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&scif_clk {
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clock-frequency = <14745600>;
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};
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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pinctrl-1 = <&sdhi0_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <&vccq_sdhi0>;
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cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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&sdhi2 {
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status = "okay";
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pinctrl-0 = <&sdhi2_pins>;
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pinctrl-names = "default";
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vmmc-supply = <&wlan_en_reg>;
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bus-width = <4>;
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non-removable;
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cap-power-off-card;
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keep-power-in-suspend;
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#address-cells = <1>;
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#size-cells = <0>;
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wlcore: wlcore@2 {
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compatible = "ti,wl1837";
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reg = <2>;
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interrupt-parent = <&gpio2>;
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&sdhi3 {
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pinctrl-0 = <&sdhi3_pins>;
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pinctrl-1 = <&sdhi3_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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bus-width = <8>;
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mmc-hs200-1_8v;
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non-removable;
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fixed-emmc-driver-type = <1>;
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status = "okay";
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};
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&usb_extal_clk {
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clock-frequency = <50000000>;
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};
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&usb2_phy0 {
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pinctrl-0 = <&usb0_pins>;
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pinctrl-names = "default";
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vbus-supply = <&vbus0_usb2>;
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status = "okay";
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};
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&usb2_phy1 {
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pinctrl-0 = <&usb1_pins>;
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pinctrl-names = "default";
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|
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status = "okay";
|
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};
|
||||
|
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&usb3_peri0 {
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phys = <&usb3_phy0>;
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phy-names = "usb";
|
||||
|
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companion = <&xhci0>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy0 {
|
||||
status = "okay";
|
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};
|
||||
|
||||
&usb3s0_clk {
|
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clock-frequency = <100000000>;
|
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};
|
||||
|
||||
&xhci0 {
|
||||
pinctrl-0 = <&usb30_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
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};
|
124
arch/arm/dts/hihope-rev4.dtsi
Normal file
124
arch/arm/dts/hihope-rev4.dtsi
Normal file
@ -0,0 +1,124 @@
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// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
|
||||
* HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "hihope-common.dtsi"
|
||||
|
||||
/ {
|
||||
audio_clkout: audio-clkout {
|
||||
/*
|
||||
* This is same as <&rcar_sound 0>
|
||||
* but needed to avoid cs2000/rcar_sound probe dead-lock
|
||||
*/
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
|
||||
wlan_en_reg: regulator-wlan_en {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "wlan-en-regulator";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
startup-delay-us = <70000>;
|
||||
|
||||
gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
x1801_clk: x1801-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
};
|
||||
|
||||
&hscif0 {
|
||||
bluetooth {
|
||||
compatible = "ti,wl1837-st";
|
||||
enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
cs2000: clk_multiplier@4f {
|
||||
#clock-cells = <0>;
|
||||
compatible = "cirrus,cs2000-cp";
|
||||
reg = <0x4f>;
|
||||
clocks = <&audio_clkout>, <&x1801_clk>;
|
||||
clock-names = "clk_in", "ref_clk";
|
||||
|
||||
assigned-clocks = <&cs2000>;
|
||||
assigned-clock-rates = <24576000>; /* 1/1 divide */
|
||||
};
|
||||
};
|
||||
|
||||
&pfc {
|
||||
i2c2_pins: i2c2 {
|
||||
groups = "i2c2_a";
|
||||
function = "i2c2";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clkout_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
|
||||
function = "ssi";
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
/* audio_clkout0/1/2/3 */
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <12288000 11289600>;
|
||||
|
||||
/* update <audio_clk_b> to <cs2000> */
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&audio_clk_a>, <&cs2000>,
|
||||
<&audio_clk_c>,
|
||||
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
|
||||
|
||||
rsnd_port: port {
|
||||
rsnd_endpoint: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_endpoint>;
|
||||
frame-master = <&rsnd_endpoint>;
|
||||
|
||||
playback = <&ssi2>;
|
||||
};
|
||||
};
|
||||
};
|
92
arch/arm/dts/hihope-rzg2-ex.dtsi
Normal file
92
arch/arm/dts/hihope-rzg2-ex.dtsi
Normal file
@ -0,0 +1,92 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet0 = &avb;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
|
||||
};
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-txid";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
pinctrl-0 = <&can0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-0 = <&can1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pciec0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
avb_pins: avb {
|
||||
mux {
|
||||
groups = "avb_link", "avb_mdio", "avb_mii";
|
||||
function = "avb";
|
||||
};
|
||||
|
||||
pins_mdio {
|
||||
groups = "avb_mdio";
|
||||
drive-strength = <24>;
|
||||
};
|
||||
|
||||
pins_mii_tx {
|
||||
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
|
||||
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
can0_pins: can0 {
|
||||
groups = "can0_data_a";
|
||||
function = "can0";
|
||||
};
|
||||
|
||||
can1_pins: can1 {
|
||||
groups = "can1_data";
|
||||
function = "can1";
|
||||
};
|
||||
|
||||
pwm0_pins: pwm0 {
|
||||
groups = "pwm0";
|
||||
function = "pwm0";
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
pinctrl-0 = <&pwm0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
21
arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts
Normal file
21
arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts
Normal file
@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 connected to
|
||||
* sub board
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a774a1-hihope-rzg2m.dts"
|
||||
#include "hihope-rzg2-ex.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HopeRun HiHope RZ/G2M with sub board";
|
||||
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m",
|
||||
"renesas,r8a774a1";
|
||||
};
|
||||
|
||||
/* SW43 should be OFF, if in ON state SATA port will be activated */
|
||||
&pciec1 {
|
||||
status = "okay";
|
||||
};
|
27
arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts
Normal file
27
arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts
Normal file
@ -0,0 +1,27 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Hihope RZ/G2M board
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#include "r8a774a1-hihope-rzg2m-ex.dts"
|
||||
#include "r8a774a1-u-boot.dtsi"
|
||||
|
||||
&gpio3 {
|
||||
bt_reg_on{
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "bt-reg-on";
|
||||
};
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
wlan_reg_on{
|
||||
gpio-hog;
|
||||
gpios = <6 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "wlan-reg-on";
|
||||
};
|
||||
};
|
37
arch/arm/dts/r8a774a1-hihope-rzg2m.dts
Normal file
37
arch/arm/dts/r8a774a1-hihope-rzg2m.dts
Normal file
@ -0,0 +1,37 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 main board
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a774a1.dtsi"
|
||||
#include "hihope-rev4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HopeRun HiHope RZ/G2M main board based on r8a774a1";
|
||||
compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1";
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
|
||||
memory@600000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x6 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&versaclock5 1>,
|
||||
<&x302_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.2",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2";
|
||||
};
|
55
arch/arm/dts/r8a774a1-u-boot.dtsi
Normal file
55
arch/arm/dts/r8a774a1-u-boot.dtsi
Normal file
@ -0,0 +1,55 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RZ/G2 R8A774A1 SoC
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&extalr_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/delete-node/ &audma0;
|
||||
/delete-node/ &audma1;
|
||||
/delete-node/ &can0;
|
||||
/delete-node/ &can1;
|
||||
/delete-node/ &canfd;
|
||||
/delete-node/ &csi20;
|
||||
/delete-node/ &csi40;
|
||||
/delete-node/ &du;
|
||||
/delete-node/ &fcpf0;
|
||||
/delete-node/ &fcpvb0;
|
||||
/delete-node/ &fcpvd0;
|
||||
/delete-node/ &fcpvd1;
|
||||
/delete-node/ &fcpvd2;
|
||||
/delete-node/ &fcpvi0;
|
||||
/delete-node/ &hdmi0;
|
||||
/delete-node/ &lvds0;
|
||||
/delete-node/ &rcar_sound;
|
||||
/delete-node/ &sdhi2;
|
||||
/delete-node/ &sound_card;
|
||||
/delete-node/ &vin0;
|
||||
/delete-node/ &vin1;
|
||||
/delete-node/ &vin2;
|
||||
/delete-node/ &vin3;
|
||||
/delete-node/ &vin4;
|
||||
/delete-node/ &vin5;
|
||||
/delete-node/ &vin6;
|
||||
/delete-node/ &vin7;
|
||||
/delete-node/ &vspb;
|
||||
/delete-node/ &vspd0;
|
||||
/delete-node/ &vspd1;
|
||||
/delete-node/ &vspd2;
|
||||
/delete-node/ &vspi0;
|
||||
|
||||
/ {
|
||||
/delete-node/ hdmi0-out;
|
||||
};
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ fdp1@fe940000;
|
||||
};
|
||||
};
|
@ -862,6 +862,9 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
|
||||
if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
|
||||
return;
|
||||
|
||||
if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL)
|
||||
priv->idma_bus_width = TMIO_SD_DMA_MODE_BUS_WIDTH;
|
||||
|
||||
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
|
||||
CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
|
||||
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
|
||||
|
@ -324,6 +324,8 @@ static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
|
||||
|
||||
tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
|
||||
|
||||
tmp |= priv->idma_bus_width;
|
||||
|
||||
if (data->flags & MMC_DATA_READ) {
|
||||
buf = data->dest;
|
||||
dir = DMA_FROM_DEVICE;
|
||||
@ -702,6 +704,7 @@ static void tmio_sd_host_init(struct tmio_sd_priv *priv)
|
||||
if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
|
||||
tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
|
||||
tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
|
||||
tmp |= priv->idma_bus_width;
|
||||
tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
|
||||
}
|
||||
}
|
||||
|
@ -90,6 +90,7 @@
|
||||
#define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */
|
||||
#define TMIO_SD_DMA_MODE 0x410
|
||||
#define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
|
||||
#define TMIO_SD_DMA_MODE_BUS_WIDTH (BIT(5) | BIT(4)) /* RCar, 64bit */
|
||||
#define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
|
||||
#define TMIO_SD_DMA_CTL 0x414
|
||||
#define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
|
||||
@ -121,6 +122,7 @@ struct tmio_sd_priv {
|
||||
unsigned int version;
|
||||
u32 caps;
|
||||
u32 read_poll_flag;
|
||||
u32 idma_bus_width;
|
||||
#define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
|
||||
#define TMIO_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
|
||||
#define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
|
||||
|
Loading…
Reference in New Issue
Block a user