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mpc85xx: Implement workaround for erratum DDR-A003
Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM. Also adding polling after enabling DDR controller to ensure completion. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -68,6 +68,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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puts("Work-around for Erratum ELBC-A001 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
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puts("Work-around for Erratum DDR-A003 enabled\n");
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#endif
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return 0;
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}
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@ -97,6 +97,82 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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temp_sdram_cfg = regs->ddr_sdram_cfg;
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temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
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out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
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if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
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out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
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out_be32(&ddr->debug[2], 0x00000400);
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out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
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out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
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out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
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out_be32(&ddr->mtcr, 0);
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out_be32(&ddr->debug[12], 0x00000015);
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out_be32(&ddr->debug[21], 0x24000000);
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out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
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out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
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asm volatile("sync;isync");
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while (!(in_be32(&ddr->debug[1]) & 0x2))
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;
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switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
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case 0x00000000:
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS0_CS1 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x02));
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break;
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case 0x00100000:
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS0_CS1 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x0a));
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break;
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case 0x00200000:
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS0_CS1 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x12));
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break;
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case 0x00300000:
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS0_CS1 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x1a));
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break;
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default:
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out_be32(&ddr->sdram_md_cntl,
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL_CS0_CS1 |
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0x04000000 |
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MD_CNTL_WRCW |
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MD_CNTL_MD_VALUE(0x02));
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printf("Unsupported RC10\n");
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break;
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}
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while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
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;
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udelay(6);
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out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
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out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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out_be32(&ddr->debug[2], 0x0);
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out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
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out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
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out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
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out_be32(&ddr->debug[12], 0x0);
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out_be32(&ddr->debug[21], 0x0);
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out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
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}
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#endif
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/*
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* For 8572 DDR1 erratum - DDR controller may enter illegal state
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* when operatiing in 32-bit bus mode with 4-beat bursts,
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@ -120,8 +196,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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asm volatile("sync;isync");
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/* Let the controller go */
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temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
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temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
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out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
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asm volatile("sync;isync");
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while (!(in_be32(&ddr->debug[1]) & 0x2))
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;
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/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
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while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
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@ -163,6 +163,7 @@
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#define CONFIG_NUM_DDR_CONTROLLERS 2
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#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
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#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
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@ -101,6 +101,25 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
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#define WR_DATA_DELAY_SHIFT 10
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#endif
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/* DDR_MD_CNTL */
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#define MD_CNTL_MD_EN 0x80000000
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#define MD_CNTL_CS_SEL_CS0 0x00000000
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#define MD_CNTL_CS_SEL_CS1 0x10000000
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#define MD_CNTL_CS_SEL_CS2 0x20000000
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#define MD_CNTL_CS_SEL_CS3 0x30000000
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#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
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#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
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#define MD_CNTL_MD_SEL_MR 0x00000000
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#define MD_CNTL_MD_SEL_EMR 0x01000000
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#define MD_CNTL_MD_SEL_EMR2 0x02000000
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#define MD_CNTL_MD_SEL_EMR3 0x03000000
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#define MD_CNTL_SET_REF 0x00800000
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#define MD_CNTL_SET_PRE 0x00400000
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#define MD_CNTL_CKE_CNTL_LOW 0x00100000
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#define MD_CNTL_CKE_CNTL_HIGH 0x00200000
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#define MD_CNTL_WRCW 0x00080000
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#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
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/* Record of register values computed */
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typedef struct fsl_ddr_cfg_regs_s {
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struct {
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