mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 07:30:26 +09:00
sharp: format
This commit is contained in:
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@ -14,72 +14,13 @@ DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_VIDEO_MXS
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static lcd_regs_t regs_early[] = {
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{ 0xff, 0, 0 }, /* EXTC Command Set Enable */
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{ 0xff, 1, 0 }, { 0x98, 1, 0 }, { 0x05, 1, 0 },
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{ 0xfd, 0, 0 }, /* PFM Type C */
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{ 0x03, 1, 0 }, { 0x13, 1, 0 }, { 0x44, 1, 0 }, { 0x00, 1, 0 },
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{ 0xf8, 0, 0 }, /* PFM Type C */
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{ 0x18, 1, 0 }, { 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x18, 1, 0 },
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{ 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 },
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{ 0x01, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
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{ 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
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{ 0xb8, 0, 0 }, /* DBI Type B Interface Setting */
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{ 0x72, 1, 0 },
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{ 0xf1, 0, 0 }, /* Gate Modulation */
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{ 0x00, 1, 0 },
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{ 0xf2, 0, 0 }, /* CR/EQ/PC */
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{ 0x00, 1, 0 }, { 0x58, 1, 0 }, { 0x40, 1, 0 },
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{ 0xfc, 0, 0 }, /* LVGL Voltage Setting? */
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{ 0x04, 1, 0 }, { 0x0f, 1, 0 }, { 0x01, 1, 0 },
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{ 0xeb, 0, 0 }, /* ? */
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{ 0x08, 1, 0 }, { 0x0f, 1, 0 },
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{ 0xe0, 0, 0 }, /* Positive Gamma Control */
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{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x35, 1, 0 }, { 0x15, 1, 0 },
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{ 0x13, 1, 0 }, { 0x16, 1, 0 }, { 0x0a, 1, 0 }, { 0x06, 1, 0 },
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{ 0x03, 1, 0 }, { 0x06, 1, 0 }, { 0x05, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x08, 1, 0 }, { 0x23, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
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{ 0xe1, 0, 0 }, /* Negative Gamma Control */
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{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x28, 1, 0 }, { 0x10, 1, 0 },
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{ 0x11, 1, 0 }, { 0x16, 1, 0 }, { 0x0b, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x02, 1, 0 }, { 0x05, 1, 0 }, { 0x04, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x08, 1, 0 }, { 0x1d, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
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{ 0xc1, 0, 0 }, /* Power Control 1 */
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{ 0x13, 1, 0 }, { 0x28, 1, 0 }, { 0x08, 1, 0 }, { 0x26, 1, 0 },
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{ 0xc7, 0, 0 }, /* VCOM Control */
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{ 0x90, 1, 0 },
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{ 0xb1, 0, 0 }, /* Frame Rate Control */
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{ 0x00, 1, 0 }, { 0x12, 1, 0 }, { 0x14, 1, 0 },
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{ 0xb4, 0, 0 }, /* Display Inversion Control */
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{ 0x02, 1, 0 },
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{ 0xbb, 0, 0 }, /* ? */
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{ 0x14, 1, 0 }, { 0x55, 1, 0 },
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{ 0x3a, 0, 0 }, /* Interface Pixel Format */
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{ 0x55, 1, 0 },
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{ 0xb6, 0, 0 }, /* MCU/RGB Interface Select */
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{ 0x01, 1, 0 }, { 0x80, 1, 0 }, { 0x8f, 1, 0 },
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{ 0x44, 0, 0 }, /* Write Tear Scan Line? */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 },
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{ 0x35, 0, 0 }, /* Tearing Effect Line On */
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{ 0x00, 1, 0 },
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};
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static lcd_regs_t regs_late[] = {
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{ 0x11, 0, 120 }, /* Sleep Out */
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{ 0x29, 0, 20 }, /* Display On */
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{ 0x2a, 0, 0 }, /* Column Address Set */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x03, 1, 0 }, { 0x1f, 1, 0 },
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{ 0x2b, 0, 0 }, /* Page Address Set */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x01, 1, 0 }, { 0xdf, 1, 0 },
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{ 0x2c, 0, 0 }, /* Memory Write*/
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};
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static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
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{
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struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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const unsigned int timeout = 0x10000;
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if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, timeout))
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if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
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timeout))
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return -ETIMEDOUT;
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writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
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@ -94,8 +35,7 @@ static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
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writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
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if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29,
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timeout))
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if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29, timeout))
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return -ETIMEDOUT;
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writel(payload, ®s->hw_lcdif_data);
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@ -106,7 +46,8 @@ static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
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void mxsfb_system_setup(void)
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{
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struct mxs_lcdif_regs *lcdif = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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struct mxs_clkctrl_regs *xtal = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct mxs_clkctrl_regs *xtal =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct mxs_pwm_regs *pwm = (struct mxs_pwm_regs *)MXS_PWM_BASE;
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int i, j;
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uint32_t valid_data;
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@ -114,13 +55,15 @@ void mxsfb_system_setup(void)
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uint8_t ili9805_mac = 0;
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lcd_config_t config = get_lcd_config();
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valid_data = readl(&lcdif->hw_lcdif_ctrl1) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK;
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valid_data = readl(&lcdif->hw_lcdif_ctrl1) &
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LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK;
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writel(0x3 << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
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&lcdif->hw_lcdif_ctrl1);
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/* Switch the LCDIF into System-Mode */
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writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
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LCDIF_CTRL_BYPASS_COUNT, &lcdif->hw_lcdif_ctrl_clr);
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LCDIF_CTRL_BYPASS_COUNT,
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&lcdif->hw_lcdif_ctrl_clr);
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writel(LCDIF_CTRL_VSYNC_MODE, &lcdif->hw_lcdif_ctrl_set);
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writel(LCDIF_VDCTRL3_VSYNC_ONLY, &lcdif->hw_lcdif_vdctrl3_set);
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@ -189,24 +132,30 @@ void mxsfb_system_setup(void)
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writel(PWM_CTRL_SFTRST, &pwm->hw_pwm_ctrl_clr);
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writel(PWM_CTRL_CLKGATE, &pwm->hw_pwm_ctrl_clr);
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writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE, &pwm->hw_pwm_ctrl_clr);
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writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE,
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&pwm->hw_pwm_ctrl_clr);
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writel((0x005a << PWM_ACTIVE0_INACTIVE_OFFSET) |
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(0x0000 << PWM_ACTIVE0_ACTIVE_OFFSET), &pwm->hw_pwm_active0_set);
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(0x0000 << PWM_ACTIVE0_ACTIVE_OFFSET),
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&pwm->hw_pwm_active0_set);
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writel((0x00f0 << PWM_ACTIVE1_INACTIVE_OFFSET) |
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(0x0000 << PWM_ACTIVE1_ACTIVE_OFFSET), &pwm->hw_pwm_active1_set);
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(0x0000 << PWM_ACTIVE1_ACTIVE_OFFSET),
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&pwm->hw_pwm_active1_set);
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writel((0x1 << PWM_PERIOD0_CDIV_OFFSET) |
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(0x2 << PWM_PERIOD0_INACTIVE_STATE_OFFSET) |
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(0x3 << PWM_PERIOD0_ACTIVE_STATE_OFFSET) |
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(0x01f3 << PWM_PERIOD0_PERIOD_OFFSET), &pwm->hw_pwm_period0_set);
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(0x01f3 << PWM_PERIOD0_PERIOD_OFFSET),
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&pwm->hw_pwm_period0_set);
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writel((0x0 << PWM_PERIOD1_CDIV_OFFSET) |
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(0x3 << PWM_PERIOD1_INACTIVE_STATE_OFFSET) |
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(0x3 << PWM_PERIOD1_ACTIVE_STATE_OFFSET) |
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(0x07cf << PWM_PERIOD1_PERIOD_OFFSET), &pwm->hw_pwm_period1_set);
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(0x07cf << PWM_PERIOD1_PERIOD_OFFSET),
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&pwm->hw_pwm_period1_set);
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writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE, &pwm->hw_pwm_ctrl_set);
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writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE,
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&pwm->hw_pwm_ctrl_set);
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}
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#endif
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@ -3,12 +3,6 @@
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#ifndef __BRAIN_LCD_H__
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#define __BRAIN_LCD_H__
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typedef struct {
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uint32_t payload;
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unsigned int data;
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uint32_t delay;
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} lcd_regs_t;
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typedef struct {
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int flip_x;
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int flip_y;
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@ -31,4 +25,74 @@ lcd_config_t get_lcd_config(void);
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#define ILI9805_MAC_MX_OFFSET 6 /* Column Address Order */
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#define ILI9805_MAC_MY_OFFSET 7 /* Row Address Order */
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typedef struct {
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uint32_t payload;
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unsigned int data;
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uint32_t delay;
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} lcd_regs_t;
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/* clang-format off */
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const static lcd_regs_t regs_early[] = {
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{ 0xff, 0, 0 }, /* EXTC Command Set Enable */
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{ 0xff, 1, 0 }, { 0x98, 1, 0 }, { 0x05, 1, 0 },
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{ 0xfd, 0, 0 }, /* PFM Type C */
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{ 0x03, 1, 0 }, { 0x13, 1, 0 }, { 0x44, 1, 0 }, { 0x00, 1, 0 },
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{ 0xf8, 0, 0 }, /* PFM Type C */
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{ 0x18, 1, 0 }, { 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x18, 1, 0 },
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{ 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 },
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{ 0x01, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
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{ 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
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{ 0xb8, 0, 0 }, /* DBI Type B Interface Setting */
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{ 0x72, 1, 0 },
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{ 0xf1, 0, 0 }, /* Gate Modulation */
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{ 0x00, 1, 0 },
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{ 0xf2, 0, 0 }, /* CR/EQ/PC */
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{ 0x00, 1, 0 }, { 0x58, 1, 0 }, { 0x40, 1, 0 },
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{ 0xfc, 0, 0 }, /* LVGL Voltage Setting? */
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{ 0x04, 1, 0 }, { 0x0f, 1, 0 }, { 0x01, 1, 0 },
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{ 0xeb, 0, 0 }, /* ? */
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{ 0x08, 1, 0 }, { 0x0f, 1, 0 },
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{ 0xe0, 0, 0 }, /* Positive Gamma Control */
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{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x35, 1, 0 }, { 0x15, 1, 0 },
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{ 0x13, 1, 0 }, { 0x16, 1, 0 }, { 0x0a, 1, 0 }, { 0x06, 1, 0 },
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{ 0x03, 1, 0 }, { 0x06, 1, 0 }, { 0x05, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x08, 1, 0 }, { 0x23, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
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{ 0xe1, 0, 0 }, /* Negative Gamma Control */
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{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x28, 1, 0 }, { 0x10, 1, 0 },
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{ 0x11, 1, 0 }, { 0x16, 1, 0 }, { 0x0b, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x02, 1, 0 }, { 0x05, 1, 0 }, { 0x04, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x08, 1, 0 }, { 0x1d, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
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{ 0xc1, 0, 0 }, /* Power Control 1 */
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{ 0x13, 1, 0 }, { 0x28, 1, 0 }, { 0x08, 1, 0 }, { 0x26, 1, 0 },
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{ 0xc7, 0, 0 }, /* VCOM Control */
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{ 0x90, 1, 0 },
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{ 0xb1, 0, 0 }, /* Frame Rate Control */
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{ 0x00, 1, 0 }, { 0x12, 1, 0 }, { 0x14, 1, 0 },
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{ 0xb4, 0, 0 }, /* Display Inversion Control */
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{ 0x02, 1, 0 },
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{ 0xbb, 0, 0 }, /* ? */
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{ 0x14, 1, 0 }, { 0x55, 1, 0 },
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{ 0x3a, 0, 0 }, /* Interface Pixel Format */
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{ 0x55, 1, 0 },
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{ 0xb6, 0, 0 }, /* MCU/RGB Interface Select */
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{ 0x01, 1, 0 }, { 0x80, 1, 0 }, { 0x8f, 1, 0 },
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{ 0x44, 0, 0 }, /* Write Tear Scan Line? */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 },
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{ 0x35, 0, 0 }, /* Tearing Effect Line On */
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{ 0x00, 1, 0 },
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};
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const static lcd_regs_t regs_late[] = {
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{ 0x11, 0, 120 }, /* Sleep Out */
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{ 0x29, 0, 20 }, /* Display On */
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{ 0x2a, 0, 0 }, /* Column Address Set */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x03, 1, 0 }, { 0x1f, 1, 0 },
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{ 0x2b, 0, 0 }, /* Page Address Set */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x01, 1, 0 }, { 0xdf, 1, 0 },
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{ 0x2c, 0, 0 }, /* Memory Write*/
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};
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/* clang-format on */
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#endif
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@ -63,18 +63,18 @@ const iomux_cfg_t iomux_setup[] = {
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MX28_PAD_ENET0_COL__GPIO_4_14 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_CRS__GPIO_4_15 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
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MX28_PAD_ENET0_TXD3__GPIO_4_12 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MX28_PAD_ENET0_TXD3__GPIO_4_12 |
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MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_TXD2__GPIO_4_11 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_RXD2__GPIO_4_9 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_TXD1__GPIO_4_8 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_TXD0__GPIO_4_7 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_TX_EN__GPIO_4_6 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_TX_CLK__GPIO_4_5 |
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MX28_PAD_ENET0_RXD1__GPIO_4_4 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | MX28_PAD_ENET0_RXD1__GPIO_4_4 |
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MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_RXD0__GPIO_4_3 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_RX_EN__GPIO_4_2| MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_RX_EN__GPIO_4_2 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_MDIO__GPIO_4_1 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_MDC__GPIO_4_0 | MUX_CONFIG_GPIO,
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@ -168,8 +168,10 @@ const iomux_cfg_t iomux_setup[] = {
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MX28_PAD_LCD_RESET__LCD_VSYNC | MUX_CONFIG_LCD,
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/* Regulator EN? */
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MX28_PAD_GPMI_ALE__GPIO_0_26 | (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_NOPULL),
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MX28_PAD_GPMI_CLE__GPIO_0_27 | (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP),
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MX28_PAD_GPMI_ALE__GPIO_0_26 |
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(MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_NOPULL),
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MX28_PAD_GPMI_CLE__GPIO_0_27 |
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(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP),
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/* ILI9805 Reset? */
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MX28_PAD_ENET_CLK__GPIO_4_16 | MUX_CONFIG_LCD,
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@ -206,7 +208,7 @@ const iomux_cfg_t iomux_setup[] = {
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(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
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(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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};
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};
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#define HW_DRAM_CTL29 (0x74 >> 2)
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#define CS_MAP 0x1
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@ -214,8 +216,8 @@ const iomux_cfg_t iomux_setup[] = {
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#define ADDR_PINS 0x1
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#define APREBIT 0xa
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#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \
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ADDR_PINS << 8 | APREBIT)
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#define HW_DRAM_CTL29_CONFIG \
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(CS_MAP << 24 | COLUMN_SIZE << 16 | ADDR_PINS << 8 | APREBIT)
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void mxs_adjust_memory_params(uint32_t *dram_vals)
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{
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@ -46,8 +46,8 @@ int board_early_init_f(void)
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#ifdef CONFIG_CMD_USB
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mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
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mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
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MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
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mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 | MXS_PAD_4MA |
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MXS_PAD_3V3 | MXS_PAD_NOPULL);
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gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
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#endif
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