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ARM: dts: Add dts files for sam9x60ek
add device tree files for sam9x60ek board with below changes. - Add initial device nodes (pmc, pinctrl, sdhc, dbgu & pit) - Add the reg property for the pinctrl node. - Add the "u-boot,dm-pre-reloc" property to determine which nodes are used by the board_init_f stage. Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com> [prasanthi.chellakumar@microchip.com: fix style/whitespace issues] Signed-off-by: Prasanthi Chellakumar <prasanthi.chellakumar@microchip.com> [nicolas.ferre@microchip.com: - fix gclk, - fix pio/pinctrl controller definition and allow to have more than only PIOA for this SoC, - removing pinctrl address] Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> [claudiu.beznea@microchip.com: - use SAM9X60's compatible for pinctrl - add drive strength and slew rate options for SDMMC0 pins.] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> [tudor.ambarus@microchip.com: - u-boot,dm-pre-reloc property in dedicated file, - fix pit len, starts from 0xFFFFFE40 and it is of len 0x10] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
This commit is contained in:
Sandeep Sheriker Mallikarjun
Eugen Hristev
parent
9cf7f46307
commit
f99e0ad25a
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@ -691,6 +691,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
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at91sam9x25ek.dtb \
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at91sam9x35ek.dtb
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dtb-$(CONFIG_TARGET_SAM9X60EK) += sam9x60ek.dtb
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dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
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dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \
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225
arch/arm/dts/sam9x60.dtsi
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225
arch/arm/dts/sam9x60.dtsi
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@ -0,0 +1,225 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
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*
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* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/at91.h>
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/{
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model = "Microchip SAM9X60 SoC";
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compatible = "microchip,sam9x60";
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aliases {
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serial0 = &dbgu;
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gpio0 = &pioA;
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gpio1 = &pioB;
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};
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clocks {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sdhci0: sdhci-host@80000000 {
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compatible = "microchip,sam9x60-sdhci";
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reg = <0x80000000 0x300>;
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clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
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clock-names = "hclock", "multclk", "baseclk";
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci0>;
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dbgu: serial@fffff200 {
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compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
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reg = <0xfffff200 0x200>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dbgu>;
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clocks = <&dbgu_clk>;
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clock-names = "usart";
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};
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pinctrl {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "microchip,sam9x60-pinctrl", "simple-bus";
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ranges = <0xfffff400 0xfffff400 0x800>;
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reg = <0xfffff400 0x200 /* pioA */
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0xfffff600 0x200 /* pioB */
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0xfffff800 0x200 /* pioC */
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0xfffffa00 0x200>; /* pioD */
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/* shared pinctrl settings */
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dbgu {
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pinctrl_dbgu: dbgu-0 {
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atmel,pins =
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<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
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AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
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};
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};
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sdhci0 {
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pinctrl_sdhci0: sdhci0 {
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atmel,pins =
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<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT /* PA17 CK periph A with pullup */
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AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 CMD periph A with pullup */
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AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA15 DAT0 periph A */
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AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 DAT1 periph A with pullup */
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AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 DAT2 periph A with pullup */
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AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 DAT3 periph A with pullup */
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};
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};
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};
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pioA: gpio@fffff400 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffff400 0x200>;
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#gpio-cells = <2>;
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gpio-controller;
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clocks = <&pioA_clk>;
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};
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pioB: gpio@fffff600 {
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compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffff600 0x200>;
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#gpio-cells = <2>;
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gpio-controller;
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clocks = <&pioB_clk>;
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};
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pmc: pmc@fffffc00 {
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compatible = "atmel,at91sam9x5-pmc";
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reg = <0xfffffc00 0x200>;
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#address-cells = <1>;
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#size-cells = <0>;
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main: mainck {
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compatible = "atmel,at91sam9x5-clk-main";
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#clock-cells = <0>;
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};
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plla: pllack {
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compatible = "microchip,sam9x60-clk-pll";
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#clock-cells = <0>;
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clocks = <&main>;
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reg = <0>;
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atmel,clk-input-range = <8000000 24000000>;
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#atmel,pll-clk-output-range-cells = <4>;
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atmel,pll-clk-output-ranges = <140000000 1200000000 0 0>;
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};
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mck: masterck {
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compatible = "atmel,at91sam9x5-clk-master";
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#clock-cells = <0>;
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clocks = <&md_slck>, <&main>, <&plla>;
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atmel,clk-output-range = <140000000 200000000>;
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atmel,clk-divisors = <1 2 4 6>;
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};
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periph: periphck {
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compatible = "microchip,sam9x60-clk-peripheral";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mck>;
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pioA_clk: pioA_clk {
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#clock-cells = <0>;
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reg = <2>;
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};
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pioB_clk: pioB_clk {
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#clock-cells = <0>;
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reg = <3>;
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};
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sdhci0_clk: sdhci0_clk {
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#clock-cells = <0>;
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reg = <12>;
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};
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dbgu_clk: dbgu_clk {
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#clock-cells = <0>;
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reg = <47>;
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};
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};
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generic: gck {
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compatible = "microchip,sam9x60-clk-generated";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&md_slck>, <&td_slck>, <&main>, <&mck>, <&plla>;
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sdhci0_gclk: sdhci0_gclk {
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#clock-cells = <0>;
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reg = <12>;
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};
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};
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};
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pit: timer@fffffe40 {
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compatible = "atmel,at91sam9260-pit";
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reg = <0xfffffe40 0x10>;
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clocks = <&mck>;
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};
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slowckc: sckc@fffffe50 {
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compatible = "atmel,at91sam9x5-sckc";
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reg = <0xfffffe50 0x4>;
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slow_osc: slow_osc {
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compatible = "atmel,at91sam9x5-clk-slow-osc";
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#clock-cells = <0>;
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clocks = <&slow_xtal>;
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};
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slow_rc_osc: slow_rc_osc {
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compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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td_slck: td_slck {
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compatible = "atmel,at91sam9x5-clk-slow";
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#clock-cells = <0>;
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clocks = <&slow_rc_osc>, <&slow_osc>;
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};
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md_slck: md_slck {
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compatible = "atmel,at91sam9x5-clk-slow";
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#clock-cells = <0>;
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clocks = <&slow_rc_osc>;
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};
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};
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};
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};
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};
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104
arch/arm/dts/sam9x60ek-u-boot.dtsi
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104
arch/arm/dts/sam9x60ek-u-boot.dtsi
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@ -0,0 +1,104 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sam9x60-u-boot.dts - Device Tree file for SAM9X60 SoC.
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*
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* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
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*/
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/ {
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chosen {
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u-boot,dm-pre-reloc;
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};
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ahb {
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u-boot,dm-pre-reloc;
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apb {
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u-boot,dm-pre-reloc;
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pinctrl {
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u-boot,dm-pre-reloc;
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};
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};
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};
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};
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&sdhci0 {
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u-boot,dm-pre-reloc;
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};
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&dbgu {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_dbgu {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_sdhci0 {
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u-boot,dm-pre-reloc;
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};
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&pioA {
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u-boot,dm-pre-reloc;
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};
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&pmc {
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u-boot,dm-pre-reloc;
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};
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&main {
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u-boot,dm-pre-reloc;
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};
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&plla {
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u-boot,dm-pre-reloc;
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};
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&mck {
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u-boot,dm-pre-reloc;
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};
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&periph {
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u-boot,dm-pre-reloc;
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};
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&pioA_clk {
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u-boot,dm-pre-reloc;
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};
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&sdhci0_clk {
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u-boot,dm-pre-reloc;
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};
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&dbgu_clk {
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u-boot,dm-pre-reloc;
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};
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&generic {
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u-boot,dm-pre-reloc;
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};
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&sdhci0_gclk {
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u-boot,dm-pre-reloc;
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};
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&slowckc {
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u-boot,dm-pre-reloc;
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};
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&slow_osc {
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u-boot,dm-pre-reloc;
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};
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&slow_rc_osc {
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u-boot,dm-pre-reloc;
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};
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&td_slck {
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u-boot,dm-pre-reloc;
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};
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&md_slck {
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u-boot,dm-pre-reloc;
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};
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19
arch/arm/dts/sam9x60ek.dts
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19
arch/arm/dts/sam9x60ek.dts
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@ -0,0 +1,19 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sam9x60ek.dts - Device Tree file for SAM9X60 EK board
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*
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* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Sandeep Sheriker M <Sandeepsheriker.mallikarjun@microchip.com>
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*/
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/dts-v1/;
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#include "sam9x60.dtsi"
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/ {
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model = "Microchip SAM9X60-Ek";
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compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9";
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chosen {
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stdout-path = &dbgu;
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};
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};
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