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ARM: DRA7xx: Enable GMAC clock control

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Enabling CPSW module by enabling GMAC clock control

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
This commit is contained in:
Mugunthan V N 2013-07-08 16:04:40 +05:30 committed by Tom Rini
parent 65e9d56fb9
commit f986d97208
3 changed files with 12 additions and 1 deletions
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7
arch/arm/cpu/armv7/omap5/hw_data.c
View File

@ -393,6 +393,9 @@ void enable_basic_clocks(void)
(*prcm)->cm_l3init_clkstctrl,
(*prcm)->cm_memif_clkstctrl,
(*prcm)->cm_l4cfg_clkstctrl,
#ifdef CONFIG_DRIVER_TI_CPSW
(*prcm)->cm_gmac_clkstctrl,
#endif
0
};
@ -420,6 +423,9 @@ void enable_basic_clocks(void)
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
(*prcm)->cm_l4per_i2c1_clkctrl,
#ifdef CONFIG_DRIVER_TI_CPSW
(*prcm)->cm_gmac_gmac_clkctrl,
#endif
0
};
@ -476,7 +482,6 @@ void enable_basic_uboot_clocks(void)
(*prcm)->cm_l3init_fsusb_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,

2
arch/arm/cpu/armv7/omap5/prcm-regs.c
View File

@ -896,6 +896,8 @@ struct prcm_regs const dra7xx_prcm = {
.cm_l3init_hsusbhost_clkctrl = 0x4a009340,
.cm_l3init_hsusbotg_clkctrl = 0x4a009348,
.cm_l3init_hsusbtll_clkctrl = 0x4a009350,
.cm_gmac_clkstctrl = 0x4a0093c0,
.cm_gmac_gmac_clkctrl = 0x4a0093d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
/* cm2.l4per */

4
arch/arm/include/asm/omap_common.h
View File

@ -340,6 +340,10 @@ struct prcm_regs {
/* SCRM stuff, used by some boards */
u32 scrm_auxclk0;
u32 scrm_auxclk1;
/* GMAC Clk Ctrl */
u32 cm_gmac_gmac_clkctrl;
u32 cm_gmac_clkstctrl;
};
struct omap_sys_ctrl_regs {