mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 17:10:42 +09:00
Merge branch 'next' of git://source.denx.de/u-boot-sh into next
- New platforms and related support
This commit is contained in:
Tom Rini
commit
f879f2621b
@ -822,6 +822,10 @@ dtb-$(CONFIG_RCAR_GEN3) += \
|
||||
r8a774a1-beacon-rzg2m-kit.dtb \
|
||||
r8a774b1-beacon-rzg2n-kit.dtb \
|
||||
r8a774e1-beacon-rzg2h-kit.dtb \
|
||||
r8a774a1-hihope-rzg2m-u-boot.dtb \
|
||||
r8a774b1-hihope-rzg2n-u-boot.dtb \
|
||||
r8a774c0-ek874-u-boot.dtb \
|
||||
r8a774e1-hihope-rzg2h-u-boot.dtb \
|
||||
r8a77950-ulcb-u-boot.dtb \
|
||||
r8a77950-salvator-x-u-boot.dtb \
|
||||
r8a77960-ulcb-u-boot.dtb \
|
||||
|
||||
64
arch/arm/dts/cat875.dtsi
Normal file
64
arch/arm/dts/cat875.dtsi
Normal file
@ -0,0 +1,64 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875)
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "Silicon Linux sub board for CAT874 (CAT875)";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &avb;
|
||||
};
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
pinctrl-0 = <&can0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-0 = <&can1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pciec0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
avb_pins: avb {
|
||||
mux {
|
||||
groups = "avb_mii";
|
||||
function = "avb";
|
||||
};
|
||||
};
|
||||
|
||||
can0_pins: can0 {
|
||||
groups = "can0_data";
|
||||
function = "can0";
|
||||
};
|
||||
|
||||
can1_pins: can1 {
|
||||
groups = "can1_data";
|
||||
function = "can1";
|
||||
};
|
||||
};
|
||||
21
arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
Normal file
21
arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
Normal file
@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to
|
||||
* sub board
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a774b1-hihope-rzg2n.dts"
|
||||
#include "hihope-rzg2-ex.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HopeRun HiHope RZ/G2N with sub board";
|
||||
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
|
||||
"renesas,r8a774b1";
|
||||
};
|
||||
|
||||
/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
27
arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
Normal file
27
arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
Normal file
@ -0,0 +1,27 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Hihope RZ/G2N board
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a774b1-hihope-rzg2n-ex.dts"
|
||||
#include "r8a774b1-u-boot.dtsi"
|
||||
|
||||
&gpio3 {
|
||||
bt_reg_on{
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "bt-reg-on";
|
||||
};
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
wlan_reg_on{
|
||||
gpio-hog;
|
||||
gpios = <6 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "wlan-reg-on";
|
||||
};
|
||||
};
|
||||
41
arch/arm/dts/r8a774b1-hihope-rzg2n.dts
Normal file
41
arch/arm/dts/r8a774b1-hihope-rzg2n.dts
Normal file
@ -0,0 +1,41 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a774b1.dtsi"
|
||||
#include "hihope-rev4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
|
||||
compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
|
||||
memory@480000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x4 0x80000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&versaclock5 1>,
|
||||
<&x302_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.3",
|
||||
"dclkin.0", "dclkin.1", "dclkin.3";
|
||||
};
|
||||
|
||||
&sdhi3 {
|
||||
mmc-hs400-1_8v;
|
||||
};
|
||||
53
arch/arm/dts/r8a774b1-u-boot.dtsi
Normal file
53
arch/arm/dts/r8a774b1-u-boot.dtsi
Normal file
@ -0,0 +1,53 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RZ/G2 R8A774B1 SoC
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&extalr_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/delete-node/ &audma0;
|
||||
/delete-node/ &audma1;
|
||||
/delete-node/ &can0;
|
||||
/delete-node/ &can1;
|
||||
/delete-node/ &canfd;
|
||||
/delete-node/ &csi20;
|
||||
/delete-node/ &csi40;
|
||||
/delete-node/ &du;
|
||||
/delete-node/ &fcpf0;
|
||||
/delete-node/ &fcpvb0;
|
||||
/delete-node/ &fcpvd0;
|
||||
/delete-node/ &fcpvd1;
|
||||
/delete-node/ &fcpvi0;
|
||||
/delete-node/ &hdmi0;
|
||||
/delete-node/ &lvds0;
|
||||
/delete-node/ &rcar_sound;
|
||||
/delete-node/ &sdhi2;
|
||||
/delete-node/ &sound_card;
|
||||
/delete-node/ &vin0;
|
||||
/delete-node/ &vin1;
|
||||
/delete-node/ &vin2;
|
||||
/delete-node/ &vin3;
|
||||
/delete-node/ &vin4;
|
||||
/delete-node/ &vin5;
|
||||
/delete-node/ &vin6;
|
||||
/delete-node/ &vin7;
|
||||
/delete-node/ &vspb;
|
||||
/delete-node/ &vspd0;
|
||||
/delete-node/ &vspd1;
|
||||
/delete-node/ &vspi0;
|
||||
|
||||
/ {
|
||||
/delete-node/ hdmi0-out;
|
||||
};
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ fdp1@fe940000;
|
||||
};
|
||||
};
|
||||
453
arch/arm/dts/r8a774c0-cat874.dts
Normal file
453
arch/arm/dts/r8a774c0-cat874.dts
Normal file
@ -0,0 +1,453 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a774c0.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/display/tda998x.h>
|
||||
|
||||
/ {
|
||||
model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
|
||||
compatible = "si-linux,cat874", "renesas,r8a774c0";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
serial1 = &hscif2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&tda19988_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led0 {
|
||||
gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED0";
|
||||
};
|
||||
|
||||
led1 {
|
||||
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED1";
|
||||
};
|
||||
|
||||
led2 {
|
||||
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED2";
|
||||
};
|
||||
|
||||
led3 {
|
||||
gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED3";
|
||||
};
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
|
||||
reg_12p0v: regulator-12p0v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D12.0V";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sound: sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,name = "CAT874 HDMI sound";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,bitclock-master = <&sndcpu>;
|
||||
simple-audio-card,frame-master = <&sndcpu>;
|
||||
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&tda19988>;
|
||||
};
|
||||
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1>, <1800000 0>;
|
||||
};
|
||||
|
||||
wlan_en_reg: fixedregulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "wlan-en-regulator";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
startup-delay-us = <70000>;
|
||||
|
||||
gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
x13_clk: x13 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
data-role = "dual";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
hs_ep: endpoint {
|
||||
remote-endpoint = <&usb3_hs_ep>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
ss_ep: endpoint {
|
||||
remote-endpoint = <&hd3ss3220_in_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&audio_clk_a {
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&x13_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&tda19988_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
&hscif2 {
|
||||
pinctrl-0 = <&hscif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "ti,wl1837-st";
|
||||
enable-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
hd3ss3220@47 {
|
||||
compatible = "ti,hd3ss3220";
|
||||
reg = <0x47>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
hd3ss3220_in_ep: endpoint {
|
||||
remote-endpoint = <&ss_ep>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
hd3ss3220_out_ep: endpoint {
|
||||
remote-endpoint = <&usb3_role_switch>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tda19988: tda19988@70 {
|
||||
compatible = "nxp,tda998x";
|
||||
reg = <0x70>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
video-ports = <0x234501>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
audio-ports = <TDA998x_I2S 0x03>;
|
||||
clocks = <&rcar_sound 1>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
tda19988_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
tda19988_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
rtc@32 {
|
||||
compatible = "epson,rx8571";
|
||||
reg = <0x32>;
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>;
|
||||
clock-names = "fck", "dclkin.0", "extal";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&pciec0 {
|
||||
/* Map all possible DDR as inbound ranges */
|
||||
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_clk_out_0", "du_sync", "du_disp",
|
||||
"du_clk_in_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
hscif2_pins: hscif2 {
|
||||
groups = "hscif2_data_a", "hscif2_ctrl_a";
|
||||
function = "hscif2";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1_b";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data_a";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi3_pins: sd3 {
|
||||
groups = "sdhi3_data4", "sdhi3_ctrl";
|
||||
function = "sdhi3";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clkout1_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi01239_ctrl", "ssi0_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
usb30_pins: usb30 {
|
||||
groups = "usb30", "usb30_id";
|
||||
function = "usb30";
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
/* audio_clkout0/1/2/3 */
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <11289600>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src0 &dvc0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi3 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdhi3_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&wlan_en_reg>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
cap-power-off-card;
|
||||
keep-power-in-suspend;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
wlcore: wlcore@2 {
|
||||
compatible = "ti,wl1837";
|
||||
reg = <2>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
renesas,no-otg-pins;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_peri0 {
|
||||
companion = <&xhci0>;
|
||||
status = "okay";
|
||||
usb-role-switch;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
usb3_hs_ep: endpoint {
|
||||
remote-endpoint = <&hs_ep>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
usb3_role_switch: endpoint {
|
||||
remote-endpoint = <&hd3ss3220_out_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&xhci0 {
|
||||
pinctrl-0 = <&usb30_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
33
arch/arm/dts/r8a774c0-ek874-u-boot.dts
Normal file
33
arch/arm/dts/r8a774c0-ek874-u-boot.dts
Normal file
@ -0,0 +1,33 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Hihope board
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronisc Corporation
|
||||
*/
|
||||
|
||||
#include "r8a774c0-ek874.dts"
|
||||
#include "r8a774c0-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
spi0 = &rpc;
|
||||
};
|
||||
};
|
||||
|
||||
&rpc {
|
||||
num-cs = <1>;
|
||||
status = "okay";
|
||||
spi-max-frequency = <50000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
flash0: spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "w25m512jv", "spi-flash", "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <1>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
14
arch/arm/dts/r8a774c0-ek874.dts
Normal file
14
arch/arm/dts/r8a774c0-ek874.dts
Normal file
@ -0,0 +1,14 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874)
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a774c0-cat874.dts"
|
||||
#include "cat875.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)";
|
||||
compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
|
||||
};
|
||||
53
arch/arm/dts/r8a774c0-u-boot.dtsi
Normal file
53
arch/arm/dts/r8a774c0-u-boot.dtsi
Normal file
@ -0,0 +1,53 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on R8A774C0 SoC
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
rpc: rpc@ee200000 {
|
||||
compatible = "renesas,rcar-gen3-rpc", "renesas,rpc-r8a774c0";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/delete-node/ &can0;
|
||||
/delete-node/ &can1;
|
||||
/delete-node/ &canfd;
|
||||
/delete-node/ &pwm0;
|
||||
/delete-node/ &pwm1;
|
||||
/delete-node/ &pwm2;
|
||||
/delete-node/ &pwm3;
|
||||
/delete-node/ &pwm4;
|
||||
/delete-node/ &pwm5;
|
||||
/delete-node/ &pwm6;
|
||||
/delete-node/ &vin4;
|
||||
/delete-node/ &vin5;
|
||||
/delete-node/ &rcar_sound;
|
||||
/delete-node/ &audma0;
|
||||
/delete-node/ &sdhi1;
|
||||
/delete-node/ &sdhi3;
|
||||
/delete-node/ &vspb0;
|
||||
/delete-node/ &vspd0;
|
||||
/delete-node/ &vspd1;
|
||||
/delete-node/ &vspi0;
|
||||
/delete-node/ &fcpvb0;
|
||||
/delete-node/ &fcpvd0;
|
||||
/delete-node/ &fcpvd1;
|
||||
/delete-node/ &fcpvi0;
|
||||
/delete-node/ &csi40;
|
||||
/delete-node/ &du;
|
||||
/delete-node/ &lvds0;
|
||||
/delete-node/ &lvds1;
|
||||
/delete-node/ &hdmi_con_out;
|
||||
/delete-node/ &sound;
|
||||
/delete-node/ &tda19988;
|
||||
@ -256,7 +256,7 @@
|
||||
resets = <&cpg 906>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
pfc: pinctrl@e6060000 {
|
||||
compatible = "renesas,pfc-r8a774c0";
|
||||
reg = <0 0xe6060000 0 0x508>;
|
||||
};
|
||||
@ -960,6 +960,7 @@
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -1214,9 +1215,8 @@
|
||||
reg = <0 0xe6ea0000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 210>;
|
||||
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
|
||||
<&dmac2 0x43>, <&dmac2 0x42>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
dmas = <&dmac0 0x43>, <&dmac0 0x42>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 210>;
|
||||
#address-cells = <1>;
|
||||
@ -1698,6 +1698,25 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec0_ep: pcie-ep@fe000000 {
|
||||
compatible = "renesas,r8a774c0-pcie-ep",
|
||||
"renesas,rcar-gen3-pcie-ep";
|
||||
reg = <0x0 0xfe000000 0 0x80000>,
|
||||
<0x0 0xfe100000 0 0x100000>,
|
||||
<0x0 0xfe200000 0 0x200000>,
|
||||
<0x0 0x30000000 0 0x8000000>,
|
||||
<0x0 0x38000000 0 0x8000000>;
|
||||
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 319>;
|
||||
clock-names = "pcie";
|
||||
resets = <&cpg 319>;
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vspb0: vsp@fe960000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe960000 0 0x8000>;
|
||||
|
||||
20
arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
Normal file
20
arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
Normal file
@ -0,0 +1,20 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the HiHope RZ/G2H sub board
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a774e1-hihope-rzg2h.dts"
|
||||
#include "hihope-rzg2-ex.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HopeRun HiHope RZ/G2H with sub board";
|
||||
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
|
||||
"renesas,r8a774e1";
|
||||
};
|
||||
|
||||
/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
27
arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
Normal file
27
arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
Normal file
@ -0,0 +1,27 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Hihope RZ/G2H board
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a774e1-hihope-rzg2h-ex.dts"
|
||||
#include "r8a774e1-u-boot.dtsi"
|
||||
|
||||
&gpio3 {
|
||||
bt_reg_on{
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "bt-reg-on";
|
||||
};
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
wlan_reg_on{
|
||||
gpio-hog;
|
||||
gpios = <6 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "wlan-reg-on";
|
||||
};
|
||||
};
|
||||
41
arch/arm/dts/r8a774e1-hihope-rzg2h.dts
Normal file
41
arch/arm/dts/r8a774e1-hihope-rzg2h.dts
Normal file
@ -0,0 +1,41 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the HiHope RZ/G2H main board
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a774e1.dtsi"
|
||||
#include "hihope-rev4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
|
||||
compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
|
||||
memory@500000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x5 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&versaclock5 1>,
|
||||
<&x302_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.3",
|
||||
"dclkin.0", "dclkin.1", "dclkin.3";
|
||||
};
|
||||
|
||||
&sdhi3 {
|
||||
mmc-hs400-1_8v;
|
||||
};
|
||||
59
arch/arm/dts/r8a774e1-u-boot.dtsi
Normal file
59
arch/arm/dts/r8a774e1-u-boot.dtsi
Normal file
@ -0,0 +1,59 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RZ/G2 R8A774E1 SoC
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&extalr_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/delete-node/ &audma0;
|
||||
/delete-node/ &audma1;
|
||||
/delete-node/ &can0;
|
||||
/delete-node/ &can1;
|
||||
/delete-node/ &canfd;
|
||||
/delete-node/ &csi20;
|
||||
/delete-node/ &csi40;
|
||||
/delete-node/ &du;
|
||||
/delete-node/ &fcpf0;
|
||||
/delete-node/ &fcpf1;
|
||||
/delete-node/ &fcpvb0;
|
||||
/delete-node/ &fcpvb1;
|
||||
/delete-node/ &fcpvd0;
|
||||
/delete-node/ &fcpvd1;
|
||||
/delete-node/ &fcpvi0;
|
||||
/delete-node/ &fcpvi1;
|
||||
/delete-node/ &hdmi0;
|
||||
/delete-node/ &lvds0;
|
||||
/delete-node/ &rcar_sound;
|
||||
/delete-node/ &sdhi2;
|
||||
/delete-node/ &sound_card;
|
||||
/delete-node/ &vin0;
|
||||
/delete-node/ &vin1;
|
||||
/delete-node/ &vin2;
|
||||
/delete-node/ &vin3;
|
||||
/delete-node/ &vin4;
|
||||
/delete-node/ &vin5;
|
||||
/delete-node/ &vin6;
|
||||
/delete-node/ &vin7;
|
||||
/delete-node/ &vspbc;
|
||||
/delete-node/ &vspbd;
|
||||
/delete-node/ &vspd0;
|
||||
/delete-node/ &vspd1;
|
||||
/delete-node/ &vspi0;
|
||||
/delete-node/ &vspi1;
|
||||
|
||||
/ {
|
||||
/delete-node/ hdmi0-out;
|
||||
};
|
||||
|
||||
/ {
|
||||
soc {
|
||||
/delete-node/ fdp1@fe940000;
|
||||
/delete-node/ fdp1@fe944000;
|
||||
};
|
||||
};
|
||||
@ -4,6 +4,8 @@ menu "Select Target SoC"
|
||||
|
||||
config R8A774A1
|
||||
bool "Renesas SoC R8A774A1"
|
||||
imply CLK_R8A774A1
|
||||
imply PINCTRL_PFC_R8A774A1
|
||||
|
||||
config R8A774B1
|
||||
bool "Renesas SoC R8A774B1"
|
||||
@ -13,6 +15,7 @@ config R8A774B1
|
||||
config R8A774C0
|
||||
bool "Renesas SoC R8A774C0"
|
||||
imply CLK_R8A774C0
|
||||
imply PINCTRL_PFC_R8A774C0
|
||||
|
||||
config R8A774E1
|
||||
bool "Renesas SoC R8A774E1"
|
||||
@ -99,6 +102,23 @@ config TARGET_EBISU
|
||||
help
|
||||
Support for Renesas R-Car Gen3 Ebisu platform
|
||||
|
||||
config TARGET_HIHOPE_RZG2
|
||||
bool "HiHope RZ/G2 board"
|
||||
imply R8A774A1
|
||||
imply R8A774B1
|
||||
imply R8A774E1
|
||||
imply SYS_MALLOC_F
|
||||
imply MULTI_DTB_FIT
|
||||
imply MULTI_DTB_FIT_USER_DEFINED_AREA
|
||||
help
|
||||
Support for RZG2 HiHope platform
|
||||
|
||||
config TARGET_SILINUX_EK874
|
||||
bool "Silicon Linux EK874 board"
|
||||
imply R8A774C0
|
||||
help
|
||||
Support for Silicon Linux EK874 platform
|
||||
|
||||
config TARGET_SALVATOR_X
|
||||
bool "Salvator-X board"
|
||||
imply R8A7795
|
||||
@ -133,12 +153,16 @@ source "board/renesas/ebisu/Kconfig"
|
||||
source "board/renesas/salvator-x/Kconfig"
|
||||
source "board/renesas/ulcb/Kconfig"
|
||||
source "board/beacon/beacon-rzg2m/Kconfig"
|
||||
source "board/hoperun/hihope-rzg2/Kconfig"
|
||||
source "board/silinux/ek874/Kconfig"
|
||||
|
||||
config MULTI_DTB_FIT_UNCOMPRESS_SZ
|
||||
default 0x80000 if TARGET_HIHOPE_RZG2
|
||||
default 0x80000 if TARGET_SALVATOR_X
|
||||
default 0x80000 if TARGET_ULCB
|
||||
|
||||
config MULTI_DTB_FIT_USER_DEF_ADDR
|
||||
default 0x49000000 if TARGET_HIHOPE_RZG2
|
||||
default 0x49000000 if TARGET_SALVATOR_X
|
||||
default 0x49000000 if TARGET_ULCB
|
||||
|
||||
|
||||
@ -22,7 +22,7 @@ cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \
|
||||
spl/u-boot-spl.srec: spl/u-boot-spl FORCE
|
||||
$(call if_changed,objcopy)
|
||||
|
||||
ifneq ($(CONFIG_R8A77990)$(CONFIG_R8A77995),)
|
||||
ifneq ($(CONFIG_R8A774C0)$(CONFIG_R8A77990)$(CONFIG_R8A77995),)
|
||||
#
|
||||
# The first 6 generate statements generate the R-Car Gen3 SCIF loader header.
|
||||
# The subsequent generate statements represent the following chunk of assembler
|
||||
|
||||
15
board/hoperun/hihope-rzg2/Kconfig
Normal file
15
board/hoperun/hihope-rzg2/Kconfig
Normal file
@ -0,0 +1,15 @@
|
||||
if TARGET_HIHOPE_RZG2
|
||||
|
||||
config SYS_SOC
|
||||
default "rmobile"
|
||||
|
||||
config SYS_BOARD
|
||||
default "hihope-rzg2"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "hoperun"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "hihope-rzg2"
|
||||
|
||||
endif
|
||||
6
board/hoperun/hihope-rzg2/MAINTAINERS
Normal file
6
board/hoperun/hihope-rzg2/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
|
||||
HIHOPE_RZG2 BOARD
|
||||
M: Biju Das <biju.das.jz@bp.renesas.com>
|
||||
S: Maintained
|
||||
F: board/hoperun/hihope-rzg2/
|
||||
F: include/configs/hihope-rzg2.h
|
||||
F: configs/hihope_rzg2_defconfig
|
||||
9
board/hoperun/hihope-rzg2/Makefile
Normal file
9
board/hoperun/hihope-rzg2/Makefile
Normal file
@ -0,0 +1,9 @@
|
||||
#
|
||||
# board/hoperun/hihope-rzg2/Makefile
|
||||
#
|
||||
# Copyright (C) 2021 Renesas Electronics Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := hihope-rzg2.o ../../renesas/rcar-common/common.o
|
||||
113
board/hoperun/hihope-rzg2/hihope-rzg2.c
Normal file
113
board/hoperun/hihope-rzg2/hihope-rzg2.c
Normal file
@ -0,0 +1,113 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* board/hoperun/hihope-rzg2/hihope-rzg2.c
|
||||
* This file is HiHope RZ/G2[HMN] board support.
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/arch/rmobile.h>
|
||||
#include <asm/arch/rcar-mstp.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/libfdt.h>
|
||||
|
||||
#define RST_BASE 0xE6160000
|
||||
#define RST_CA57RESCNT (RST_BASE + 0x40)
|
||||
#define RST_CA53RESCNT (RST_BASE + 0x44)
|
||||
#define RST_CA57_CODE 0xA5A5000F
|
||||
#define RST_CA53_CODE 0x5A5A000F
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
|
||||
|
||||
/* HSUSB block registers */
|
||||
#define HSUSB_REG_LPSTS 0xE6590102
|
||||
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
|
||||
#define HSUSB_REG_UGCTRL2 0xE6590184
|
||||
#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
|
||||
#define HSUSB_REG_UGCTRL2_RESERVED_3 0x1 /* bit[3:0] should be B'0001 */
|
||||
|
||||
#define PRR_REGISTER (0xFFF00044)
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
|
||||
|
||||
/* Configure the HSUSB block */
|
||||
mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
|
||||
/*
|
||||
* We need to add a barrier instruction after HSUSB module stop release.
|
||||
* This barrier instruction can be either reading back the same MSTP
|
||||
* register or any other register in the same IP block. So like linux
|
||||
* adding check for MSTPSR register, which indicates the clock has been
|
||||
* started.
|
||||
*/
|
||||
for (i = 1000; i > 0; --i) {
|
||||
if (!(readl(MSTPSR7) & HSUSB_MSTP704))
|
||||
break;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
/* Select EHCI/OHCI host module for USB2.0 ch0 */
|
||||
writel(HSUSB_REG_UGCTRL2_USB0SEL_EHCI | HSUSB_REG_UGCTRL2_RESERVED_3,
|
||||
HSUSB_REG_UGCTRL2);
|
||||
/* low power status */
|
||||
setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
unsigned long midr, cputype;
|
||||
|
||||
asm volatile("mrs %0, midr_el1" : "=r" (midr));
|
||||
cputype = (midr >> 4) & 0xfff;
|
||||
|
||||
if (cputype == 0xd03)
|
||||
writel(RST_CA53_CODE, RST_CA53RESCNT);
|
||||
else
|
||||
writel(RST_CA57_CODE, RST_CA57RESCNT);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MULTI_DTB_FIT)
|
||||
/* If the firmware passed a device tree, use it for board identification. */
|
||||
extern u64 rcar_atf_boot_args[];
|
||||
|
||||
static bool is_hoperun_hihope_rzg2_board(const char *board_name)
|
||||
{
|
||||
void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
|
||||
bool ret = false;
|
||||
|
||||
if ((fdt_magic(atf_fdt_blob) == FDT_MAGIC) &&
|
||||
(fdt_node_check_compatible(atf_fdt_blob, 0, board_name) == 0))
|
||||
ret = true;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2m") &&
|
||||
!strcmp(name, "r8a774a1-hihope-rzg2m-u-boot"))
|
||||
return 0;
|
||||
|
||||
if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2n") &&
|
||||
!strcmp(name, "r8a774b1-hihope-rzg2n-u-boot"))
|
||||
return 0;
|
||||
|
||||
if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2h") &&
|
||||
!strcmp(name, "r8a774e1-hihope-rzg2h-u-boot"))
|
||||
return 0;
|
||||
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
15
board/silinux/ek874/Kconfig
Normal file
15
board/silinux/ek874/Kconfig
Normal file
@ -0,0 +1,15 @@
|
||||
if TARGET_SILINUX_EK874
|
||||
|
||||
config SYS_SOC
|
||||
default "rmobile"
|
||||
|
||||
config SYS_BOARD
|
||||
default "ek874"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "silinux"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "silinux-ek874"
|
||||
|
||||
endif
|
||||
6
board/silinux/ek874/MAINTAINERS
Normal file
6
board/silinux/ek874/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
|
||||
SILINUX_EK874 BOARD
|
||||
M: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
|
||||
S: Maintained
|
||||
F: board/silinux/ek874/
|
||||
F: include/configs/silinux-ek874.h
|
||||
F: configs/silinux_ek874_defconfig
|
||||
13
board/silinux/ek874/Makefile
Normal file
13
board/silinux/ek874/Makefile
Normal file
@ -0,0 +1,13 @@
|
||||
#
|
||||
# board/silinux/ek874/Makefile
|
||||
#
|
||||
# Copyright (C) 2021 Renesas Electronics Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y := ../../renesas/rcar-common/gen3-spl.o
|
||||
else
|
||||
obj-y := ek874.o ../../renesas/rcar-common/common.o
|
||||
endif
|
||||
30
board/silinux/ek874/ek874.c
Normal file
30
board/silinux/ek874/ek874.c
Normal file
@ -0,0 +1,30 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* board/silinux/ek874/ek874.c
|
||||
* This file is ek874 board support.
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define RST_BASE 0xE6160000
|
||||
#define RST_CA53RESCNT (RST_BASE + 0x44)
|
||||
#define RST_CA53_CODE 0x5A5A000F
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
writel(RST_CA53_CODE, RST_CA53RESCNT);
|
||||
}
|
||||
82
configs/hihope_rzg2_defconfig
Normal file
82
configs/hihope_rzg2_defconfig
Normal file
@ -0,0 +1,82 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_TEXT_BASE=0x50000000
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_OFFSET=0xFFFE0000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_HIHOPE_RZG2=y
|
||||
# CONFIG_SPL is not set
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-hihope-rzg2m-u-boot"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
|
||||
CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m.dtb"
|
||||
# CONFIG_BOARD_EARLY_INIT_F is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot r8a774b1-hihope-rzg2n-u-boot r8a774e1-hihope-rzg2h-u-boot"
|
||||
CONFIG_MULTI_DTB_FIT_LZO=y
|
||||
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=1
|
||||
CONFIG_SYS_MMC_ENV_PART=2
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_RENESAS=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_IIC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_RENESAS_SDHI=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_USE_4K_SECTORS=y
|
||||
CONFIG_BITBANGMII=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_RENESAS_RAVB=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_RENESAS_RPC_SPI=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
83
configs/silinux_ek874_defconfig
Normal file
83
configs/silinux_ek874_defconfig
Normal file
@ -0,0 +1,83 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_TEXT_BASE=0x50000000
|
||||
CONFIG_SPL_TEXT_BASE=0xe6318000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x3F0000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_SILINUX_EK874=y
|
||||
# CONFIG_BOARD_EARLY_INIT_F is not set
|
||||
CONFIG_SOC_DEVICE=y
|
||||
CONFIG_SOC_DEVICE_RENESAS=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a774c0-ek874-u-boot"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_FIT=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_DEFAULT_FDT_FILE="r8a774c0-ek874.dtb"
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_BLK=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_RENESAS=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_IIC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_USE_4K_SECTORS=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_RENESAS_RPC_SPI=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_RENESAS_SDHI=y
|
||||
CONFIG_BITBANGMII=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_RENESAS_RAVB=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
@ -77,6 +77,16 @@ config PINCTRL_PFC_R8A774B1
|
||||
the GPIO definitions and pin control functions for each available
|
||||
multiplex function.
|
||||
|
||||
config PINCTRL_PFC_R8A774C0
|
||||
bool "Renesas RZ/G2 R8A774C0 pin control driver"
|
||||
depends on PINCTRL_PFC
|
||||
help
|
||||
Support pin multiplexing control on Renesas RZ/G2E R8A774C0 SoCs.
|
||||
|
||||
The driver is controlled by a device tree node which contains both
|
||||
the GPIO definitions and pin control functions for each available
|
||||
multiplex function.
|
||||
|
||||
config PINCTRL_PFC_R8A774E1
|
||||
bool "Renesas RZ/G2 R8A774E1 pin control driver"
|
||||
depends on PINCTRL_PFC
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
obj-$(CONFIG_PINCTRL_PFC) += pfc.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A774C0) += pfc-r8a77990.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a7795.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
|
||||
|
||||
@ -1603,6 +1603,7 @@ static const unsigned int canfd1_data_mux[] = {
|
||||
CANFD1_TX_MARK, CANFD1_RX_MARK,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
/* - DRIF0 --------------------------------------------------------------- */
|
||||
static const unsigned int drif0_ctrl_a_pins[] = {
|
||||
/* CLK, SYNC */
|
||||
@ -1795,6 +1796,7 @@ static const unsigned int drif3_data1_b_pins[] = {
|
||||
static const unsigned int drif3_data1_b_mux[] = {
|
||||
RIF3_D1_B_MARK,
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
|
||||
|
||||
/* - DU --------------------------------------------------------------------- */
|
||||
static const unsigned int du_rgb666_pins[] = {
|
||||
@ -2818,6 +2820,57 @@ static const unsigned int pwm6_b_mux[] = {
|
||||
PWM6_B_MARK,
|
||||
};
|
||||
|
||||
/* - QSPI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi0_ctrl_pins[] = {
|
||||
/* QSPI0_SPCLK, QSPI0_SSL */
|
||||
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5),
|
||||
};
|
||||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
|
||||
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
|
||||
/* QSPI0_IO2, QSPI0_IO3 */
|
||||
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
|
||||
};
|
||||
/* - QSPI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi1_ctrl_pins[] = {
|
||||
/* QSPI1_SPCLK, QSPI1_SSL */
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11),
|
||||
};
|
||||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
/* QSPI1_IO2, QSPI1_IO3 */
|
||||
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif0_data_a_pins[] = {
|
||||
/* RX, TX */
|
||||
@ -3770,8 +3823,10 @@ static const unsigned int vin5_clk_b_mux[] = {
|
||||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_pin_group common[247];
|
||||
struct sh_pfc_pin_group common[253];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
struct sh_pfc_pin_group automotive[21];
|
||||
#endif
|
||||
} pinmux_groups = {
|
||||
.common = {
|
||||
SH_PFC_PIN_GROUP(audio_clk_a),
|
||||
@ -3916,6 +3971,12 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(pwm5_b),
|
||||
SH_PFC_PIN_GROUP(pwm6_a),
|
||||
SH_PFC_PIN_GROUP(pwm6_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
SH_PFC_PIN_GROUP(scif0_data_a),
|
||||
SH_PFC_PIN_GROUP(scif0_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif0_ctrl_a),
|
||||
@ -4022,6 +4083,7 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(vin5_clk_a),
|
||||
SH_PFC_PIN_GROUP(vin5_clk_b),
|
||||
},
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
.automotive = {
|
||||
SH_PFC_PIN_GROUP(drif0_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(drif0_data0_a),
|
||||
@ -4045,6 +4107,7 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(drif3_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data1_b),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
|
||||
};
|
||||
|
||||
static const char * const audio_clk_groups[] = {
|
||||
@ -4098,6 +4161,7 @@ static const char * const canfd1_groups[] = {
|
||||
"canfd1_data",
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
static const char * const drif0_groups[] = {
|
||||
"drif0_ctrl_a",
|
||||
"drif0_data0_a",
|
||||
@ -4130,6 +4194,7 @@ static const char * const drif3_groups[] = {
|
||||
"drif3_data0_b",
|
||||
"drif3_data1_b",
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
|
||||
|
||||
static const char * const du_groups[] = {
|
||||
"du_rgb666",
|
||||
@ -4315,6 +4380,18 @@ static const char * const pwm6_groups[] = {
|
||||
"pwm6_b",
|
||||
};
|
||||
|
||||
static const char * const qspi0_groups[] = {
|
||||
"qspi0_ctrl",
|
||||
"qspi0_data2",
|
||||
"qspi0_data4",
|
||||
};
|
||||
|
||||
static const char * const qspi1_groups[] = {
|
||||
"qspi1_ctrl",
|
||||
"qspi1_data2",
|
||||
"qspi1_data4",
|
||||
};
|
||||
|
||||
static const char * const scif0_groups[] = {
|
||||
"scif0_data_a",
|
||||
"scif0_clk_a",
|
||||
@ -4469,8 +4546,10 @@ static const char * const vin5_groups[] = {
|
||||
};
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_function common[47];
|
||||
struct sh_pfc_function common[49];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
struct sh_pfc_function automotive[4];
|
||||
#endif
|
||||
} pinmux_functions = {
|
||||
.common = {
|
||||
SH_PFC_FUNCTION(audio_clk),
|
||||
@ -4504,6 +4583,8 @@ static const struct {
|
||||
SH_PFC_FUNCTION(pwm4),
|
||||
SH_PFC_FUNCTION(pwm5),
|
||||
SH_PFC_FUNCTION(pwm6),
|
||||
SH_PFC_FUNCTION(qspi0),
|
||||
SH_PFC_FUNCTION(qspi1),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif2),
|
||||
@ -4521,12 +4602,14 @@ static const struct {
|
||||
SH_PFC_FUNCTION(vin4),
|
||||
SH_PFC_FUNCTION(vin5),
|
||||
},
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
.automotive = {
|
||||
SH_PFC_FUNCTION(drif0),
|
||||
SH_PFC_FUNCTION(drif1),
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77990 */
|
||||
};
|
||||
|
||||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
|
||||
@ -34,6 +34,7 @@ enum sh_pfc_model {
|
||||
SH_PFC_R8A7796,
|
||||
SH_PFC_R8A774A1,
|
||||
SH_PFC_R8A774B1,
|
||||
SH_PFC_R8A774C0,
|
||||
SH_PFC_R8A774E1,
|
||||
SH_PFC_R8A77965,
|
||||
SH_PFC_R8A77970,
|
||||
@ -927,6 +928,10 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
|
||||
if (model == SH_PFC_R8A774B1)
|
||||
priv->pfc.info = &r8a774b1_pinmux_info;
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A774C0
|
||||
if (model == SH_PFC_R8A774C0)
|
||||
priv->pfc.info = &r8a774c0_pinmux_info;
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
|
||||
if (model == SH_PFC_R8A774E1)
|
||||
priv->pfc.info = &r8a774e1_pinmux_info;
|
||||
@ -1014,6 +1019,12 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = {
|
||||
.data = SH_PFC_R8A774B1,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A774C0
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a774c0",
|
||||
.data = SH_PFC_R8A774C0,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a774e1",
|
||||
|
||||
@ -295,6 +295,7 @@ sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
|
||||
|
||||
extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
|
||||
|
||||
20
include/configs/hihope-rzg2.h
Normal file
20
include/configs/hihope-rzg2.h
Normal file
@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* include/configs/hihope-rzg2.h
|
||||
* This file is HOPERUN HiHope RZ/G2 board configuration.
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#ifndef __HIHOPE_RZG2_H
|
||||
#define __HIHOPE_RZG2_H
|
||||
|
||||
#include "rcar-gen3-common.h"
|
||||
|
||||
/* Ethernet RAVB */
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
/* Generic Timer Definitions (use in assembler source) */
|
||||
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
|
||||
|
||||
#endif /* __HIHOPE_RZG2_H */
|
||||
20
include/configs/silinux-ek874.h
Normal file
20
include/configs/silinux-ek874.h
Normal file
@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* include/configs/silinux-ek874.h
|
||||
* This file is Silicon Linux EK874 board configuration.
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#ifndef __SILINUX_EK874_H
|
||||
#define __SILINUX_EK874_H
|
||||
|
||||
#include "rcar-gen3-common.h"
|
||||
|
||||
/* Ethernet RAVB */
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
/* Generic Timer Definitions (use in assembler source) */
|
||||
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
|
||||
|
||||
#endif /* __SILINUX_EK874_H */
|
||||
8
include/dt-bindings/display/tda998x.h
Normal file
8
include/dt-bindings/display/tda998x.h
Normal file
@ -0,0 +1,8 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _DT_BINDINGS_TDA998X_H
|
||||
#define _DT_BINDINGS_TDA998X_H
|
||||
|
||||
#define TDA998x_SPDIF 1
|
||||
#define TDA998x_I2S 2
|
||||
|
||||
#endif /*_DT_BINDINGS_TDA998X_H */
|
||||
Loading…
Reference in New Issue
Block a user