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arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe
- Enabling GTR lane-0 to PCIe - Enabling PCIe node in device tree Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -168,7 +168,7 @@
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gtr_sel0 {
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gtr_sel0 {
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gpio-hog;
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gpio-hog;
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gpios = <0 0>;
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gpios = <0 0>;
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output-high; /* PCIE = 0, DP = 1 */
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output-low; /* PCIE = 0, DP = 1 */
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line-name = "sel0";
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line-name = "sel0";
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};
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};
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gtr_sel1 {
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gtr_sel1 {
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@ -551,7 +551,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
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};
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};
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&pcie {
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&pcie {
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/* status = "okay"; */
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status = "okay";
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};
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};
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&qspi {
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&qspi {
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