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https://github.com/brain-hackers/u-boot-brain
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mpc83xx: Lindent and clean up cpu/mpc83xx/speed.c
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@ -224,10 +224,11 @@ int get_clocks (void)
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return -8;
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}
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if (usbmph_clk != 0
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&& usbdr_clk != 0
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&& usbmph_clk != usbdr_clk ) {
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/* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */
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if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
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/* if USB MPH clock is not disabled and
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* USB DR clock is not disabled then
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* USB MPH & USB DR must have the same rate
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*/
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return -9;
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}
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#endif
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@ -254,7 +255,8 @@ int get_clocks (void)
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return -6;
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}
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#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
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lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
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lbiu_clk = csb_clk *
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(1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
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#else
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#error Unknown MPC83xx chip
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#endif
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@ -270,10 +272,12 @@ int get_clocks (void)
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return -10;
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}
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#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
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ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
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ddr_clk = csb_clk *
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(1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
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corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
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#if defined (CONFIG_MPC8360)
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ddr_sec_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
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ddr_sec_clk = csb_clk * (1 +
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((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
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#endif
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#else
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#error Unknown MPC83xx chip
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@ -344,7 +348,6 @@ ulong get_ddr_clk(ulong dummy)
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return gd->ddr_clk;
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}
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/********************************************
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* get_bus_freq
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* return system bus freq in Hz
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