mpc83xx: Lindent and clean up cpu/mpc83xx/speed.c

This commit is contained in:
Kim Phillips 2006-11-02 19:47:11 -06:00
parent 90f30a710a
commit f7fb2e703e

View File

@ -224,10 +224,11 @@ int get_clocks (void)
return -8;
}
if (usbmph_clk != 0
&& usbdr_clk != 0
&& usbmph_clk != usbdr_clk ) {
/* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */
if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
/* if USB MPH clock is not disabled and
* USB DR clock is not disabled then
* USB MPH & USB DR must have the same rate
*/
return -9;
}
#endif
@ -254,7 +255,8 @@ int get_clocks (void)
return -6;
}
#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
lbiu_clk = csb_clk *
(1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
#else
#error Unknown MPC83xx chip
#endif
@ -270,10 +272,12 @@ int get_clocks (void)
return -10;
}
#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
ddr_clk = csb_clk *
(1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
#if defined (CONFIG_MPC8360)
ddr_sec_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
ddr_sec_clk = csb_clk * (1 +
((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
#endif
#else
#error Unknown MPC83xx chip
@ -344,7 +348,6 @@ ulong get_ddr_clk(ulong dummy)
return gd->ddr_clk;
}
/********************************************
* get_bus_freq
* return system bus freq in Hz