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https://github.com/brain-hackers/u-boot-brain
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mpc83xx: Lindent and clean up cpu/mpc83xx/speed.c
This commit is contained in:
Kim Phillips
parent
90f30a710a
commit
f7fb2e703e
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@ -53,38 +53,38 @@ typedef enum {
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typedef struct {
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mult_t core_csb_ratio;
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mult_t vco_divider;
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mult_t vco_divider;
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} corecnf_t;
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corecnf_t corecnf_tab[] = {
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{ _byp, _byp}, /* 0x00 */
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{ _byp, _byp}, /* 0x01 */
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{ _byp, _byp}, /* 0x02 */
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{ _byp, _byp}, /* 0x03 */
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{ _byp, _byp}, /* 0x04 */
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{ _byp, _byp}, /* 0x05 */
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{ _byp, _byp}, /* 0x06 */
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{ _byp, _byp}, /* 0x07 */
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{ _1x, _x2}, /* 0x08 */
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{ _1x, _x4}, /* 0x09 */
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{ _1x, _x8}, /* 0x0A */
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{ _1x, _x8}, /* 0x0B */
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{_1_5x, _x2}, /* 0x0C */
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{_1_5x, _x4}, /* 0x0D */
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{_1_5x, _x8}, /* 0x0E */
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{_1_5x, _x8}, /* 0x0F */
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{ _2x, _x2}, /* 0x10 */
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{ _2x, _x4}, /* 0x11 */
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{ _2x, _x8}, /* 0x12 */
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{ _2x, _x8}, /* 0x13 */
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{_2_5x, _x2}, /* 0x14 */
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{_2_5x, _x4}, /* 0x15 */
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{_2_5x, _x8}, /* 0x16 */
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{_2_5x, _x8}, /* 0x17 */
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{ _3x, _x2}, /* 0x18 */
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{ _3x, _x4}, /* 0x19 */
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{ _3x, _x8}, /* 0x1A */
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{ _3x, _x8}, /* 0x1B */
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{_byp, _byp}, /* 0x00 */
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{_byp, _byp}, /* 0x01 */
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{_byp, _byp}, /* 0x02 */
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{_byp, _byp}, /* 0x03 */
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{_byp, _byp}, /* 0x04 */
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{_byp, _byp}, /* 0x05 */
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{_byp, _byp}, /* 0x06 */
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{_byp, _byp}, /* 0x07 */
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{_1x, _x2}, /* 0x08 */
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{_1x, _x4}, /* 0x09 */
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{_1x, _x8}, /* 0x0A */
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{_1x, _x8}, /* 0x0B */
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{_1_5x, _x2}, /* 0x0C */
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{_1_5x, _x4}, /* 0x0D */
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{_1_5x, _x8}, /* 0x0E */
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{_1_5x, _x8}, /* 0x0F */
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{_2x, _x2}, /* 0x10 */
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{_2x, _x4}, /* 0x11 */
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{_2x, _x8}, /* 0x12 */
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{_2x, _x8}, /* 0x13 */
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{_2_5x, _x2}, /* 0x14 */
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{_2_5x, _x4}, /* 0x15 */
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{_2_5x, _x8}, /* 0x16 */
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{_2_5x, _x8}, /* 0x17 */
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{_3x, _x2}, /* 0x18 */
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{_3x, _x4}, /* 0x19 */
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{_3x, _x8}, /* 0x1A */
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{_3x, _x8}, /* 0x1B */
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};
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/* ----------------------------------------------------------------- */
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@ -92,15 +92,15 @@ corecnf_t corecnf_tab[] = {
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/*
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*
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*/
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int get_clocks (void)
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int get_clocks(void)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
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volatile immap_t *im = (immap_t *) CFG_IMMRBAR;
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u32 pci_sync_in;
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u8 spmf;
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u8 clkin_div;
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u8 spmf;
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u8 clkin_div;
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u32 sccr;
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u32 corecnf_tab_index;
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u8 corepll;
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u8 corepll;
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u32 lcrr;
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u32 csb_clk;
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@ -125,7 +125,7 @@ int get_clocks (void)
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u32 brg_clk;
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#endif
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
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@ -224,17 +224,18 @@ int get_clocks (void)
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return -8;
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}
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if (usbmph_clk != 0
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&& usbdr_clk != 0
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&& usbmph_clk != usbdr_clk ) {
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/* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */
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if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
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/* if USB MPH clock is not disabled and
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* USB DR clock is not disabled then
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* USB MPH & USB DR must have the same rate
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*/
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return -9;
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}
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#endif
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#if defined (CONFIG_MPC8360)
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i2c1_clk = csb_clk;
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#endif
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i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
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i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
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switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
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case 0:
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@ -254,7 +255,8 @@ int get_clocks (void)
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return -6;
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}
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#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
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lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
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lbiu_clk = csb_clk *
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(1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
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#else
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#error Unknown MPC83xx chip
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#endif
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@ -270,17 +272,19 @@ int get_clocks (void)
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return -10;
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}
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#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
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ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
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ddr_clk = csb_clk *
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(1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
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corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
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#if defined (CONFIG_MPC8360)
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ddr_sec_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
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ddr_sec_clk = csb_clk * (1 +
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((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
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#endif
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#else
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#error Unknown MPC83xx chip
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#endif
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corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
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if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) {
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if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
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/* corecnf_tab_index is too high, possibly worng value */
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return -11;
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}
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@ -297,7 +301,7 @@ int get_clocks (void)
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core_clk = 2 * csb_clk;
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break;
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case _2_5x:
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core_clk = ( 5 * csb_clk) / 2;
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core_clk = (5 * csb_clk) / 2;
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break;
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case _3x:
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core_clk = 3 * csb_clk;
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@ -310,31 +314,31 @@ int get_clocks (void)
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#if defined (CONFIG_MPC8360)
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qepmf = (im->reset.rcwl & RCWL_CEPMF) >> RCWL_CEPMF_SHIFT;
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qepdf = (im->reset.rcwl & RCWL_CEPDF) >> RCWL_CEPDF_SHIFT;
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qe_clk = (pci_sync_in * qepmf)/(1+qepdf);
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qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
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brg_clk = qe_clk / 2;
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#endif
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gd->csb_clk = csb_clk;
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gd->csb_clk = csb_clk;
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#if defined(CONFIG_MPC8349)
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gd->tsec1_clk = tsec1_clk;
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gd->tsec2_clk = tsec2_clk;
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gd->usbmph_clk = usbmph_clk;
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gd->usbdr_clk = usbdr_clk;
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gd->tsec1_clk = tsec1_clk;
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gd->tsec2_clk = tsec2_clk;
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gd->usbmph_clk = usbmph_clk;
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gd->usbdr_clk = usbdr_clk;
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#endif
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gd->core_clk = core_clk;
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gd->i2c1_clk = i2c1_clk;
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gd->i2c2_clk = i2c2_clk;
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gd->enc_clk = enc_clk;
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gd->lbiu_clk = lbiu_clk;
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gd->lclk_clk = lclk_clk;
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gd->ddr_clk = ddr_clk;
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gd->core_clk = core_clk;
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gd->i2c1_clk = i2c1_clk;
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gd->i2c2_clk = i2c2_clk;
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gd->enc_clk = enc_clk;
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gd->lbiu_clk = lbiu_clk;
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gd->lclk_clk = lclk_clk;
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gd->ddr_clk = ddr_clk;
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#if defined (CONFIG_MPC8360)
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gd->ddr_sec_clk = ddr_sec_clk;
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gd->qe_clk = qe_clk;
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gd->brg_clk = brg_clk;
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gd->qe_clk = qe_clk;
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gd->brg_clk = brg_clk;
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#endif
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gd->cpu_clk = gd->core_clk;
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gd->bus_clk = gd->csb_clk;
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gd->cpu_clk = gd->core_clk;
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gd->bus_clk = gd->csb_clk;
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return 0;
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}
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@ -344,38 +348,37 @@ ulong get_ddr_clk(ulong dummy)
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return gd->ddr_clk;
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}
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/********************************************
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* get_bus_freq
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* return system bus freq in Hz
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*********************************************/
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ulong get_bus_freq (ulong dummy)
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ulong get_bus_freq(ulong dummy)
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{
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return gd->csb_clk;
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}
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int print_clock_conf (void)
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int print_clock_conf(void)
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{
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printf("Clock configuration:\n");
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printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
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printf(" Core: %4d MHz\n",gd->core_clk/1000000);
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printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
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printf(" Core: %4d MHz\n", gd->core_clk / 1000000);
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#if defined (CONFIG_MPC8360)
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printf(" QE: %4d MHz\n",gd->qe_clk/1000000);
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printf(" QE: %4d MHz\n", gd->qe_clk / 1000000);
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#endif
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printf(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
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printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000);
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printf(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
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printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
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printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
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printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000);
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#if defined (CONFIG_MPC8360)
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printf(" DDR Secondary: %4d MHz\n",gd->ddr_sec_clk/1000000);
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printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000);
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#endif
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printf(" SEC: %4d MHz\n",gd->enc_clk/1000000);
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printf(" I2C1: %4d MHz\n",gd->i2c1_clk/1000000);
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printf(" I2C2: %4d MHz\n",gd->i2c2_clk/1000000);
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printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
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printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
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printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
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#if defined(CONFIG_MPC8349)
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printf(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
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printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
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printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
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printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
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printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
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printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);
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printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000);
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printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000);
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#endif
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return 0;
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}
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