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kirkwood: define CONFIG_SYS_CACHELINE_SIZE
By default, on Kirkwood SoC DCache Lnd ICache line lengths are 32 bytes long Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
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#include <asm/arch/kirkwood.h>
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#include <asm/arch/kirkwood.h>
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#define CONFIG_ARM926EJS 1 /* Basic Architecture */
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#define CONFIG_ARM926EJS 1 /* Basic Architecture */
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#define CONFIG_SYS_CACHELINE_SIZE 32
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/* default Dcache Line length for kirkwood */
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#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
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#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
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#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
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#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
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#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
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#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
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