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ARM: k2g: add a workaround to reset the phy

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This patch adds a workaround to reset the phy one time during boot
using GPIO0 pin 10 to make sure, the Phy latches the configuration
from the input pins correctly.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Murali Karicheri 2019-02-21 12:02:04 -05:00 committed by Tom Rini
parent 55d5cb1728
commit f748ec9d32
2 changed files with 18 additions and 0 deletions
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3
arch/arm/mach-keystone/include/mach/hardware-k2g.h
View File

@ -69,9 +69,12 @@
#define K2G_GPIO0_BASE 0X02603000
#define K2G_GPIO1_BASE 0X0260a000
#define K2G_GPIO0_BANK0_BASE K2G_GPIO0_BASE + 0x10
#define K2G_GPIO1_BANK2_BASE K2G_GPIO1_BASE + 0x38
#define K2G_GPIO_DIR_OFFSET 0x0
#define K2G_GPIO_OUTDATA_OFFSET 0x4
#define K2G_GPIO_SETDATA_OFFSET 0x8
#define K2G_GPIO_CLRDATA_OFFSET 0xC
/* BOOTCFG RESETMUX8 */
#define KS2_RSTMUX8 (KS2_DEVICE_STATE_CTRL_BASE + 0x328)

15
board/ti/ks2_evm/board_k2g.c
View File

@ -315,6 +315,21 @@ int embedded_dtb_select(void)
BIT(9));
setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
BIT(9));
} else if (board_is_k2g_ice()) {
/* GBE Phy workaround. For Phy to latch the input
* configuration, a GPIO reset is asserted at the
* Phy reset pin to latch configuration correctly after SoC
* reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
* board. Just do a low to high transition.
*/
clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
BIT(10));
setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
BIT(10));
/* Delay just to get a transition to high */
udelay(100);
setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
BIT(10));
}
return 0;