mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
video: atmel/lcd: add LCD driver for new Atmel SoC
The new Atmel SoC (at91sam9x5 series and at91sam9n12) add a totally different LCD controller. Add this new driver to support it. Using CONFIG_ATMEL_HLCD (distinguish with CONFIG_ATMEL_LCD) to enable this in board configuration file. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Bo Shen
Anatolij Gustschin
parent
bfd4be803b
commit
f6b690e65c
|
|
@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
|
|||
LIB := $(obj)libvideo.o
|
||||
|
||||
COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
|
||||
COBJS-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
|
||||
COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
|
||||
COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
|
||||
COBJS-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
|
||||
|
|
|
|||
211
drivers/video/atmel_hlcdfb.c
Normal file
211
drivers/video/atmel_hlcdfb.c
Normal file
|
|
@ -0,0 +1,211 @@
|
|||
/*
|
||||
* Driver for AT91/AT32 MULTI LAYER LCD Controller
|
||||
*
|
||||
* Copyright (C) 2012 Atmel Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <lcd.h>
|
||||
#include <atmel_hlcdc.h>
|
||||
|
||||
int lcd_line_length;
|
||||
int lcd_color_fg;
|
||||
int lcd_color_bg;
|
||||
|
||||
void *lcd_base; /* Start of framebuffer memory */
|
||||
void *lcd_console_address; /* Start of console buffer */
|
||||
|
||||
short console_col;
|
||||
short console_row;
|
||||
|
||||
/* configurable parameters */
|
||||
#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
|
||||
#define ATMEL_LCDC_DMA_BURST_LEN 8
|
||||
#ifndef ATMEL_LCDC_GUARD_TIME
|
||||
#define ATMEL_LCDC_GUARD_TIME 1
|
||||
#endif
|
||||
|
||||
#define ATMEL_LCDC_FIFO_SIZE 512
|
||||
|
||||
#define lcdc_readl(reg) __raw_readl((reg))
|
||||
#define lcdc_writel(reg, val) __raw_writel((val), (reg))
|
||||
|
||||
void lcd_ctrl_init(void *lcdbase)
|
||||
{
|
||||
unsigned long value;
|
||||
struct lcd_dma_desc *desc;
|
||||
struct atmel_hlcd_regs *regs;
|
||||
|
||||
if (!has_lcdc())
|
||||
return; /* No lcdc */
|
||||
|
||||
regs = (struct atmel_hlcd_regs *)panel_info.mmio;
|
||||
|
||||
/* Disable DISP signal */
|
||||
lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS);
|
||||
while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
|
||||
udelay(1);
|
||||
/* Disable synchronization */
|
||||
lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS);
|
||||
while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
|
||||
udelay(1);
|
||||
/* Disable pixel clock */
|
||||
lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_CLKDIS);
|
||||
while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
|
||||
udelay(1);
|
||||
/* Disable PWM */
|
||||
lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_PWMDIS);
|
||||
while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
|
||||
udelay(1);
|
||||
|
||||
/* Set pixel clock */
|
||||
value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
|
||||
if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
|
||||
value++;
|
||||
|
||||
if (value < 1) {
|
||||
/* Using system clock as pixel clock */
|
||||
lcdc_writel(®s->lcdc_lcdcfg0,
|
||||
LCDC_LCDCFG0_CLKDIV(0)
|
||||
| LCDC_LCDCFG0_CGDISHCR
|
||||
| LCDC_LCDCFG0_CGDISHEO
|
||||
| LCDC_LCDCFG0_CGDISOVR1
|
||||
| LCDC_LCDCFG0_CGDISBASE
|
||||
| panel_info.vl_clk_pol
|
||||
| LCDC_LCDCFG0_CLKSEL);
|
||||
|
||||
} else {
|
||||
lcdc_writel(®s->lcdc_lcdcfg0,
|
||||
LCDC_LCDCFG0_CLKDIV(value - 2)
|
||||
| LCDC_LCDCFG0_CGDISHCR
|
||||
| LCDC_LCDCFG0_CGDISHEO
|
||||
| LCDC_LCDCFG0_CGDISOVR1
|
||||
| LCDC_LCDCFG0_CGDISBASE
|
||||
| panel_info.vl_clk_pol);
|
||||
}
|
||||
|
||||
/* Initialize control register 5 */
|
||||
value = 0;
|
||||
|
||||
value |= panel_info.vl_sync;
|
||||
|
||||
#ifndef LCD_OUTPUT_BPP
|
||||
/* Output is 24bpp */
|
||||
value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
|
||||
#else
|
||||
switch (LCD_OUTPUT_BPP) {
|
||||
case 12:
|
||||
value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
|
||||
break;
|
||||
case 16:
|
||||
value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
|
||||
break;
|
||||
case 18:
|
||||
value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
|
||||
break;
|
||||
case 24:
|
||||
value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
|
||||
value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
|
||||
lcdc_writel(®s->lcdc_lcdcfg5, value);
|
||||
|
||||
/* Vertical & Horizontal Timing */
|
||||
value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
|
||||
value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
|
||||
lcdc_writel(®s->lcdc_lcdcfg1, value);
|
||||
|
||||
value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin);
|
||||
value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1);
|
||||
lcdc_writel(®s->lcdc_lcdcfg2, value);
|
||||
|
||||
value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1);
|
||||
value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1);
|
||||
lcdc_writel(®s->lcdc_lcdcfg3, value);
|
||||
|
||||
/* Display size */
|
||||
value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
|
||||
value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
|
||||
lcdc_writel(®s->lcdc_lcdcfg4, value);
|
||||
|
||||
lcdc_writel(®s->lcdc_basecfg0,
|
||||
LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO);
|
||||
|
||||
switch (NBITS(panel_info.vl_bpix)) {
|
||||
case 16:
|
||||
lcdc_writel(®s->lcdc_basecfg1,
|
||||
LCDC_BASECFG1_RGBMODE_16BPP_RGB_565);
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
|
||||
lcdc_writel(®s->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0));
|
||||
lcdc_writel(®s->lcdc_basecfg3, 0);
|
||||
lcdc_writel(®s->lcdc_basecfg4, LCDC_BASECFG4_DMA);
|
||||
|
||||
/* Disable all interrupts */
|
||||
lcdc_writel(®s->lcdc_lcdidr, ~0UL);
|
||||
lcdc_writel(®s->lcdc_baseidr, ~0UL);
|
||||
|
||||
/* Setup the DMA descriptor, this descriptor will loop to itself */
|
||||
desc = (struct lcd_dma_desc *)(lcdbase - 16);
|
||||
|
||||
desc->address = (u32)lcdbase;
|
||||
/* Disable DMA transfer interrupt & descriptor loaded interrupt. */
|
||||
desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
|
||||
| LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
|
||||
desc->next = (u32)desc;
|
||||
|
||||
lcdc_writel(®s->lcdc_baseaddr, desc->address);
|
||||
lcdc_writel(®s->lcdc_basectrl, desc->control);
|
||||
lcdc_writel(®s->lcdc_basenext, desc->next);
|
||||
lcdc_writel(®s->lcdc_basecher, LCDC_BASECHER_CHEN |
|
||||
LCDC_BASECHER_UPDATEEN);
|
||||
|
||||
/* Enable LCD */
|
||||
value = lcdc_readl(®s->lcdc_lcden);
|
||||
lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_CLKEN);
|
||||
while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
|
||||
udelay(1);
|
||||
value = lcdc_readl(®s->lcdc_lcden);
|
||||
lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_SYNCEN);
|
||||
while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
|
||||
udelay(1);
|
||||
value = lcdc_readl(®s->lcdc_lcden);
|
||||
lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_DISPEN);
|
||||
while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
|
||||
udelay(1);
|
||||
value = lcdc_readl(®s->lcdc_lcden);
|
||||
lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN);
|
||||
while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
|
||||
udelay(1);
|
||||
}
|
||||
231
include/atmel_hlcdc.h
Normal file
231
include/atmel_hlcdc.h
Normal file
|
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Header file for AT91/AT32 MULTI LAYER LCD Controller
|
||||
*
|
||||
* Data structure and register user interface
|
||||
*
|
||||
* Copyright (C) 2012 Atmel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ATMEL_HLCDC_H__
|
||||
#define __ATMEL_HLCDC_H__
|
||||
|
||||
/* Atmel multi layer lcdc hardware registers */
|
||||
struct atmel_hlcd_regs {
|
||||
u32 lcdc_lcdcfg0;
|
||||
u32 lcdc_lcdcfg1;
|
||||
u32 lcdc_lcdcfg2;
|
||||
u32 lcdc_lcdcfg3;
|
||||
u32 lcdc_lcdcfg4;
|
||||
u32 lcdc_lcdcfg5;
|
||||
u32 lcdc_lcdcfg6;
|
||||
u32 res1;
|
||||
u32 lcdc_lcden;
|
||||
u32 lcdc_lcddis;
|
||||
u32 lcdc_lcdsr;
|
||||
u32 res2;
|
||||
u32 lcdc_lcdidr;
|
||||
u32 res3[3];
|
||||
u32 lcdc_basecher;
|
||||
u32 res4[3];
|
||||
u32 lcdc_baseidr;
|
||||
u32 res5[3];
|
||||
u32 lcdc_baseaddr;
|
||||
u32 lcdc_basectrl;
|
||||
u32 lcdc_basenext;
|
||||
u32 lcdc_basecfg0;
|
||||
u32 lcdc_basecfg1;
|
||||
u32 lcdc_basecfg2;
|
||||
u32 lcdc_basecfg3;
|
||||
u32 lcdc_basecfg4;
|
||||
};
|
||||
|
||||
#define LCDC_LCDCFG0_CLKPOL (0x1 << 0)
|
||||
#define LCDC_LCDCFG0_CLKSEL (0x1 << 2)
|
||||
#define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3)
|
||||
#define LCDC_LCDCFG0_CGDISBASE (0x1 << 8)
|
||||
#define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9)
|
||||
#define LCDC_LCDCFG0_CGDISHEO (0x1 << 11)
|
||||
#define LCDC_LCDCFG0_CGDISHCR (0x1 << 12)
|
||||
#define LCDC_LCDCFG0_CLKDIV_Pos 16
|
||||
#define LCDC_LCDCFG0_CLKDIV_Msk (0xff << LCDC_LCDCFG0_CLKDIV_Pos)
|
||||
#define LCDC_LCDCFG0_CLKDIV(value) \
|
||||
((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos)))
|
||||
|
||||
#define LCDC_LCDCFG1_HSPW_Pos 0
|
||||
#define LCDC_LCDCFG1_HSPW_Msk (0x3f << LCDC_LCDCFG1_HSPW_Pos)
|
||||
#define LCDC_LCDCFG1_HSPW(value) \
|
||||
((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos)))
|
||||
#define LCDC_LCDCFG1_VSPW_Pos 16
|
||||
#define LCDC_LCDCFG1_VSPW_Msk (0x3f << LCDC_LCDCFG1_VSPW_Pos)
|
||||
#define LCDC_LCDCFG1_VSPW(value) \
|
||||
((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos)))
|
||||
|
||||
#define LCDC_LCDCFG2_VFPW_Pos 0
|
||||
#define LCDC_LCDCFG2_VFPW_Msk (0x3f << LCDC_LCDCFG2_VFPW_Pos)
|
||||
#define LCDC_LCDCFG2_VFPW(value) \
|
||||
((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos)))
|
||||
#define LCDC_LCDCFG2_VBPW_Pos 16
|
||||
#define LCDC_LCDCFG2_VBPW_Msk (0x3f << LCDC_LCDCFG2_VBPW_Pos)
|
||||
#define LCDC_LCDCFG2_VBPW(value) \
|
||||
((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos)))
|
||||
|
||||
#define LCDC_LCDCFG3_HFPW_Pos 0
|
||||
#define LCDC_LCDCFG3_HFPW_Msk (0xff << LCDC_LCDCFG3_HFPW_Pos)
|
||||
#define LCDC_LCDCFG3_HFPW(value) \
|
||||
((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos)))
|
||||
#define LCDC_LCDCFG3_HBPW_Pos 16
|
||||
#define LCDC_LCDCFG3_HBPW_Msk (0xff << LCDC_LCDCFG3_HBPW_Pos)
|
||||
#define LCDC_LCDCFG3_HBPW(value) \
|
||||
((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos)))
|
||||
|
||||
#define LCDC_LCDCFG4_PPL_Pos 0
|
||||
#define LCDC_LCDCFG4_PPL_Msk (0x7ff << LCDC_LCDCFG4_PPL_Pos)
|
||||
#define LCDC_LCDCFG4_PPL(value) \
|
||||
((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos)))
|
||||
#define LCDC_LCDCFG4_RPF_Pos 16
|
||||
#define LCDC_LCDCFG4_RPF_Msk (0x7ff << LCDC_LCDCFG4_RPF_Pos)
|
||||
#define LCDC_LCDCFG4_RPF(value) \
|
||||
((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos)))
|
||||
|
||||
#define LCDC_LCDCFG5_HSPOL (0x1 << 0)
|
||||
#define LCDC_LCDCFG5_VSPOL (0x1 << 1)
|
||||
#define LCDC_LCDCFG5_VSPDLYS (0x1 << 2)
|
||||
#define LCDC_LCDCFG5_VSPDLYE (0x1 << 3)
|
||||
#define LCDC_LCDCFG5_DISPPOL (0x1 << 4)
|
||||
#define LCDC_LCDCFG5_SERIAL (0x1 << 5)
|
||||
#define LCDC_LCDCFG5_DITHER (0x1 << 6)
|
||||
#define LCDC_LCDCFG5_DISPDLY (0x1 << 7)
|
||||
#define LCDC_LCDCFG5_MODE_Pos 8
|
||||
#define LCDC_LCDCFG5_MODE_Msk (0x3 << LCDC_LCDCFG5_MODE_Pos)
|
||||
#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0 << 8)
|
||||
#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1 << 8)
|
||||
#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2 << 8)
|
||||
#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3 << 8)
|
||||
#define LCDC_LCDCFG5_VSPSU (0x1 << 12)
|
||||
#define LCDC_LCDCFG5_VSPHO (0x1 << 13)
|
||||
#define LCDC_LCDCFG5_GUARDTIME_Pos 16
|
||||
#define LCDC_LCDCFG5_GUARDTIME_Msk (0x1f << LCDC_LCDCFG5_GUARDTIME_Pos)
|
||||
#define LCDC_LCDCFG5_GUARDTIME(value) \
|
||||
((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos)))
|
||||
|
||||
#define LCDC_LCDCFG6_PWMPS_Pos 0
|
||||
#define LCDC_LCDCFG6_PWMPS_Msk (0x7 << LCDC_LCDCFG6_PWMPS_Pos)
|
||||
#define LCDC_LCDCFG6_PWMPS(value) \
|
||||
((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos)))
|
||||
#define LCDC_LCDCFG6_PWMPOL (0x1 << 4)
|
||||
#define LCDC_LCDCFG6_PWMCVAL_Pos 8
|
||||
#define LCDC_LCDCFG6_PWMCVAL_Msk (0xff << LCDC_LCDCFG6_PWMCVAL_Pos)
|
||||
#define LCDC_LCDCFG6_PWMCVAL(value) \
|
||||
((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos)))
|
||||
|
||||
#define LCDC_LCDEN_CLKEN (0x1 << 0)
|
||||
#define LCDC_LCDEN_SYNCEN (0x1 << 1)
|
||||
#define LCDC_LCDEN_DISPEN (0x1 << 2)
|
||||
#define LCDC_LCDEN_PWMEN (0x1 << 3)
|
||||
|
||||
#define LCDC_LCDDIS_CLKDIS (0x1 << 0)
|
||||
#define LCDC_LCDDIS_SYNCDIS (0x1 << 1)
|
||||
#define LCDC_LCDDIS_DISPDIS (0x1 << 2)
|
||||
#define LCDC_LCDDIS_PWMDIS (0x1 << 3)
|
||||
#define LCDC_LCDDIS_CLKRST (0x1 << 8)
|
||||
#define LCDC_LCDDIS_SYNCRST (0x1 << 9)
|
||||
#define LCDC_LCDDIS_DISPRST (0x1 << 10)
|
||||
#define LCDC_LCDDIS_PWMRST (0x1 << 11)
|
||||
|
||||
#define LCDC_LCDSR_CLKSTS (0x1 << 0)
|
||||
#define LCDC_LCDSR_LCDSTS (0x1 << 1)
|
||||
#define LCDC_LCDSR_DISPSTS (0x1 << 2)
|
||||
#define LCDC_LCDSR_PWMSTS (0x1 << 3)
|
||||
#define LCDC_LCDSR_SIPSTS (0x1 << 4)
|
||||
|
||||
#define LCDC_LCDIDR_SOFID (0x1 << 0)
|
||||
#define LCDC_LCDIDR_DISID (0x1 << 1)
|
||||
#define LCDC_LCDIDR_DISPID (0x1 << 2)
|
||||
#define LCDC_LCDIDR_FIFOERRID (0x1 << 4)
|
||||
#define LCDC_LCDIDR_BASEID (0x1 << 8)
|
||||
#define LCDC_LCDIDR_OVR1ID (0x1 << 9)
|
||||
#define LCDC_LCDIDR_HEOID (0x1 << 11)
|
||||
#define LCDC_LCDIDR_HCRID (0x1 << 12)
|
||||
|
||||
#define LCDC_BASECHER_CHEN (0x1 << 0)
|
||||
#define LCDC_BASECHER_UPDATEEN (0x1 << 1)
|
||||
#define LCDC_BASECHER_A2QEN (0x1 << 2)
|
||||
|
||||
#define LCDC_BASEIDR_DMA (0x1 << 2)
|
||||
#define LCDC_BASEIDR_DSCR (0x1 << 3)
|
||||
#define LCDC_BASEIDR_ADD (0x1 << 4)
|
||||
#define LCDC_BASEIDR_DONE (0x1 << 5)
|
||||
#define LCDC_BASEIDR_OVR (0x1 << 6)
|
||||
|
||||
#define LCDC_BASECTRL_DFETCH (0x1 << 0)
|
||||
#define LCDC_BASECTRL_LFETCH (0x1 << 1)
|
||||
#define LCDC_BASECTRL_DMAIEN (0x1 << 2)
|
||||
#define LCDC_BASECTRL_DSCRIEN (0x1 << 3)
|
||||
#define LCDC_BASECTRL_ADDIEN (0x1 << 4)
|
||||
#define LCDC_BASECTRL_DONEIEN (0x1 << 5)
|
||||
|
||||
#define LCDC_BASECFG0_BLEN_Pos 4
|
||||
#define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0 << 4)
|
||||
#define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1 << 4)
|
||||
#define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2 << 4)
|
||||
#define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3 << 4)
|
||||
#define LCDC_BASECFG0_DLBO (0x1 << 8)
|
||||
|
||||
#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4)
|
||||
#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4)
|
||||
#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4)
|
||||
#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4)
|
||||
#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4)
|
||||
#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4)
|
||||
#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4)
|
||||
#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4)
|
||||
#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4)
|
||||
#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4)
|
||||
#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4)
|
||||
#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4)
|
||||
#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4)
|
||||
#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4)
|
||||
|
||||
#define LCDC_BASECFG2_XSTRIDE_Pos 0
|
||||
#define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos)
|
||||
#define LCDC_BASECFG2_XSTRIDE(value) \
|
||||
((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos)))
|
||||
|
||||
#define LCDC_BASECFG3_BDEF_Pos 0
|
||||
#define LCDC_BASECFG3_BDEF_Msk (0xff << LCDC_BASECFG3_BDEF_Pos)
|
||||
#define LCDC_BASECFG3_BDEF(value) \
|
||||
((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos)))
|
||||
#define LCDC_BASECFG3_GDEF_Pos 8
|
||||
#define LCDC_BASECFG3_GDEF_Msk (0xff << LCDC_BASECFG3_GDEF_Pos)
|
||||
#define LCDC_BASECFG3_GDEF(value) \
|
||||
((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos)))
|
||||
#define LCDC_BASECFG3_RDEF_Pos 16
|
||||
#define LCDC_BASECFG3_RDEF_Msk (0xff << LCDC_BASECFG3_RDEF_Pos)
|
||||
#define LCDC_BASECFG3_RDEF(value) \
|
||||
((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))
|
||||
|
||||
#define LCDC_BASECFG4_DMA (0x1 << 8)
|
||||
#define LCDC_BASECFG4_REP (0x1 << 9)
|
||||
|
||||
struct lcd_dma_desc {
|
||||
u32 address;
|
||||
u32 control;
|
||||
u32 next;
|
||||
};
|
||||
|
||||
#define ATMEL_LCDC_LUT(n) (0x0400 + ((n)*4))
|
||||
|
||||
#endif /* __ATMEL_HLCDC_H__ */
|
||||
|
|
@ -158,7 +158,7 @@ typedef struct vidinfo {
|
|||
struct pxafb_info pxa;
|
||||
} vidinfo_t;
|
||||
|
||||
#elif defined(CONFIG_ATMEL_LCD)
|
||||
#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
|
||||
|
||||
typedef struct vidinfo {
|
||||
ushort vl_col; /* Number of columns (i.e. 640) */
|
||||
|
|
@ -170,6 +170,7 @@ typedef struct vidinfo {
|
|||
u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
|
||||
u_long vl_tft; /* 0 = passive, 1 = TFT */
|
||||
u_long vl_cont_pol_low; /* contrast polarity is low */
|
||||
u_long vl_clk_pol; /* clock polarity */
|
||||
|
||||
/* Horizontal control register. */
|
||||
u_long vl_hsync_len; /* Length of horizontal sync */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user