mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 23:50:26 +09:00
aspeed: Board init functions and common configs for ast2500 based boards
Add configuration file with parameters that are very likely to be shared by all ast2500-based boards. Add ast2500-board.c file with the init code that is very likely to be shared by all ast2500-based boards. Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
14e4b14979
commit
f6a6a9f049
@ -5,4 +5,4 @@
|
||||
#
|
||||
|
||||
obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o
|
||||
obj-$(CONFIG_ASPEED_AST2500) += ast2500/
|
||||
obj-$(CONFIG_ASPEED_AST2500) += ast2500/ ast2500-board.o
|
||||
|
83
arch/arm/mach-aspeed/ast2500-board.c
Normal file
83
arch/arm/mach-aspeed/ast2500-board.c
Normal file
@ -0,0 +1,83 @@
|
||||
/*
|
||||
* Copyright (c) 2016 Google, Inc
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <ram.h>
|
||||
#include <timer.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/timer.h>
|
||||
#include <asm/arch/wdt.h>
|
||||
#include <linux/err.h>
|
||||
#include <dm/uclass.h>
|
||||
|
||||
/*
|
||||
* Second Watchdog Timer by default is configured
|
||||
* to trigger secondary boot source.
|
||||
*/
|
||||
#define AST_2ND_BOOT_WDT 1
|
||||
|
||||
/*
|
||||
* Third Watchdog Timer by default is configured
|
||||
* to toggle Flash address mode switch before reset.
|
||||
*/
|
||||
#define AST_FLASH_ADDR_DETECT_WDT 2
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void lowlevel_init(void)
|
||||
{
|
||||
/*
|
||||
* These two watchdogs need to be stopped as soon as possible,
|
||||
* otherwise the board might hang. By default they are set to
|
||||
* a very short timeout and even simple debug write to serial
|
||||
* console early in the init process might cause them to fire.
|
||||
*/
|
||||
struct ast_wdt *flash_addr_wdt =
|
||||
(struct ast_wdt *)(WDT_BASE +
|
||||
sizeof(struct ast_wdt) *
|
||||
AST_FLASH_ADDR_DETECT_WDT);
|
||||
|
||||
clrbits_le32(&flash_addr_wdt->ctrl, WDT_CTRL_EN);
|
||||
|
||||
#ifndef CONFIG_FIRMWARE_2ND_BOOT
|
||||
struct ast_wdt *sec_boot_wdt =
|
||||
(struct ast_wdt *)(WDT_BASE +
|
||||
sizeof(struct ast_wdt) *
|
||||
AST_2ND_BOOT_WDT);
|
||||
|
||||
clrbits_le32(&sec_boot_wdt->ctrl, WDT_CTRL_EN);
|
||||
#endif
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
struct ram_info ram;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
|
||||
if (ret) {
|
||||
debug("DRAM FAIL1\r\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = ram_get_info(dev, &ram);
|
||||
if (ret) {
|
||||
debug("DRAM FAIL2\r\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
gd->ram_size = ram.size;
|
||||
|
||||
return 0;
|
||||
}
|
81
include/configs/aspeed-common.h
Normal file
81
include/configs/aspeed-common.h
Normal file
@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2020 ASPEED Technology Inc.
|
||||
* Ryan Chen <ryan_chen@aspeedtech.com>
|
||||
*
|
||||
* Copyright 2016 IBM Corporation
|
||||
* (C) Copyright 2016 Google, Inc
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __AST_COMMON_CONFIG_H
|
||||
#define __AST_COMMON_CONFIG_H
|
||||
|
||||
/* Misc CPU related */
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/* Enable cache controller */
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||
|
||||
#ifdef CONFIG_PRE_CON_BUF_SZ
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR (0x1e720000 + CONFIG_PRE_CON_BUF_SZ)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE (36*1024 - CONFIG_PRE_CON_BUF_SZ)
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR (0x1e720000)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE (36*1024)
|
||||
#endif
|
||||
|
||||
#define SYS_INIT_RAM_END (CONFIG_SYS_INIT_RAM_ADDR \
|
||||
+ CONFIG_SYS_INIT_RAM_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \
|
||||
- GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
|
||||
+ sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_BOOTARGS \
|
||||
"console=ttyS4,115200n8" \
|
||||
" root=/dev/ram rw"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"verify=yes\0" \
|
||||
"spi_dma=yes\0" \
|
||||
""
|
||||
|
||||
#endif /* __AST_COMMON_CONFIG_H */
|
Loading…
Reference in New Issue
Block a user