mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 00:50:43 +09:00
85xx: Add the concept of CFG_CCSRBAR_PHYS
When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
parent
5b5eb9ca5b
commit
f69766e4b5
@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe210_0000 1M PCI2 IO
|
* 0xe210_0000 1M PCI2 IO
|
||||||
* 0xe300_0000 1M PCIe IO
|
* 0xe300_0000 1M PCIe IO
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||||
};
|
};
|
||||||
|
@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe000_0000 1M CCSRBAR
|
* 0xe000_0000 1M CCSRBAR
|
||||||
* 0xe200_0000 16M PCI1 IO
|
* 0xe200_0000 16M PCI1 IO
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||||
|
|
||||||
|
@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe200_0000 16M PCI1 IO
|
* 0xe200_0000 16M PCI1 IO
|
||||||
* 0xe300_0000 16M PCI2 IO
|
* 0xe300_0000 16M PCI2 IO
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||||
|
|
||||||
|
@ -75,7 +75,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe000_0000 1M CCSRBAR
|
* 0xe000_0000 1M CCSRBAR
|
||||||
* 0xe100_0000 255M PCI IO range
|
* 0xe100_0000 255M PCI IO range
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 4, BOOKE_PAGESZ_64M, 1),
|
0, 4, BOOKE_PAGESZ_64M, 1),
|
||||||
|
|
||||||
|
@ -80,7 +80,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe210_0000 1M PCI2 IO
|
* 0xe210_0000 1M PCI2 IO
|
||||||
* 0xe300_0000 1M PCIe IO
|
* 0xe300_0000 1M PCIe IO
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||||
|
|
||||||
|
@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe200_0000 16M PCI1 IO
|
* 0xe200_0000 16M PCI1 IO
|
||||||
* 0xe300_0000 16M PCI2 IO
|
* 0xe300_0000 16M PCI2 IO
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||||
|
|
||||||
|
@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe000_0000 1M CCSRBAR
|
* 0xe000_0000 1M CCSRBAR
|
||||||
* 0xe200_0000 16M PCI1 IO
|
* 0xe200_0000 16M PCI1 IO
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||||
|
|
||||||
|
@ -74,7 +74,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe200_0000 8M PCI1 IO
|
* 0xe200_0000 8M PCI1 IO
|
||||||
* 0xe280_0000 8M PCIe IO
|
* 0xe280_0000 8M PCIe IO
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 3, BOOKE_PAGESZ_64M, 1),
|
0, 3, BOOKE_PAGESZ_64M, 1),
|
||||||
|
|
||||||
|
@ -27,7 +27,7 @@
|
|||||||
#include <asm/mmu.h>
|
#include <asm/mmu.h>
|
||||||
|
|
||||||
struct fsl_e_tlb_entry tlb_table[] = {
|
struct fsl_e_tlb_entry tlb_table[] = {
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
0, 1, BOOKE_PAGESZ_1M, 1),
|
||||||
|
|
||||||
|
@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe000_0000 1M CCSRBAR
|
* 0xe000_0000 1M CCSRBAR
|
||||||
* 0xe200_0000 16M PCI1 IO
|
* 0xe200_0000 16M PCI1 IO
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||||
|
|
||||||
|
@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe000_0000 1M CCSRBAR
|
* 0xe000_0000 1M CCSRBAR
|
||||||
* 0xe200_0000 16M PCI1 IO
|
* 0xe200_0000 16M PCI1 IO
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||||
|
|
||||||
|
@ -81,7 +81,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe0000000 1M CCSRBAR
|
* 0xe0000000 1M CCSRBAR
|
||||||
* 0xe2000000 16M PCI1 IO
|
* 0xe2000000 16M PCI1 IO
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 4, BOOKE_PAGESZ_64M, 1),
|
0, 4, BOOKE_PAGESZ_64M, 1),
|
||||||
|
|
||||||
|
@ -28,7 +28,7 @@
|
|||||||
|
|
||||||
struct fsl_e_tlb_entry tlb_table[] = {
|
struct fsl_e_tlb_entry tlb_table[] = {
|
||||||
/* TLB for CCSRBAR (IMMR) */
|
/* TLB for CCSRBAR (IMMR) */
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
0, 1, BOOKE_PAGESZ_1M, 1),
|
||||||
|
|
||||||
|
@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe000_0000 1M CCSRBAR
|
* 0xe000_0000 1M CCSRBAR
|
||||||
* 0xe200_0000 16M PCI1 IO
|
* 0xe200_0000 16M PCI1 IO
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||||
|
|
||||||
|
@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe200_0000 16M PCI1 IO
|
* 0xe200_0000 16M PCI1 IO
|
||||||
* 0xe300_0000 16M PCI2 IO
|
* 0xe300_0000 16M PCI2 IO
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 5, BOOKE_PAGESZ_64M, 1),
|
0, 5, BOOKE_PAGESZ_64M, 1),
|
||||||
|
|
||||||
|
@ -91,7 +91,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
|
|||||||
* 0xe000_0000 1M CCSRBAR
|
* 0xe000_0000 1M CCSRBAR
|
||||||
* 0xe200_0000 16M PCI1 IO
|
* 0xe200_0000 16M PCI1 IO
|
||||||
*/
|
*/
|
||||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
|
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
0, 6, BOOKE_PAGESZ_64M, 1),
|
0, 6, BOOKE_PAGESZ_64M, 1),
|
||||||
|
|
||||||
|
@ -127,12 +127,12 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
|
|||||||
/* We run cpu_init_early_f in AS = 1 */
|
/* We run cpu_init_early_f in AS = 1 */
|
||||||
void cpu_init_early_f(void)
|
void cpu_init_early_f(void)
|
||||||
{
|
{
|
||||||
set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR,
|
set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||||
1, 0, BOOKE_PAGESZ_4K, 0);
|
1, 0, BOOKE_PAGESZ_4K, 0);
|
||||||
|
|
||||||
/* set up CCSR if we want it moved */
|
/* set up CCSR if we want it moved */
|
||||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
|
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS)
|
||||||
{
|
{
|
||||||
u32 temp;
|
u32 temp;
|
||||||
|
|
||||||
@ -141,7 +141,7 @@ void cpu_init_early_f(void)
|
|||||||
1, 1, BOOKE_PAGESZ_4K, 0);
|
1, 1, BOOKE_PAGESZ_4K, 0);
|
||||||
|
|
||||||
temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT);
|
temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT);
|
||||||
out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR >> 12);
|
out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12);
|
||||||
|
|
||||||
temp = in_be32((volatile u32 *)CFG_CCSRBAR);
|
temp = in_be32((volatile u32 *)CFG_CCSRBAR);
|
||||||
}
|
}
|
||||||
|
@ -96,6 +96,7 @@
|
|||||||
*/
|
*/
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
|
#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
|
||||||
|
@ -100,6 +100,7 @@
|
|||||||
*/
|
*/
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
|
|
||||||
|
@ -83,6 +83,7 @@
|
|||||||
*/
|
*/
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||||
|
@ -82,6 +82,7 @@ extern unsigned long get_clock_freq(void);
|
|||||||
*/
|
*/
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -98,6 +98,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|||||||
*/
|
*/
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
|
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
|
||||||
|
@ -96,6 +96,7 @@ extern unsigned long get_clock_freq(void);
|
|||||||
*/
|
*/
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
|
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
|
||||||
|
@ -82,6 +82,7 @@ extern unsigned long get_clock_freq(void);
|
|||||||
*/
|
*/
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -95,6 +95,7 @@
|
|||||||
*/
|
*/
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
|
|
||||||
|
@ -90,6 +90,7 @@ extern unsigned long get_clock_freq(void);
|
|||||||
*/
|
*/
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
|
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
|
||||||
|
@ -92,6 +92,7 @@
|
|||||||
*/
|
*/
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
|
|
||||||
|
@ -94,6 +94,7 @@
|
|||||||
*/
|
*/
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
|
|
||||||
|
@ -99,6 +99,7 @@
|
|||||||
#else
|
#else
|
||||||
#define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
|
#define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
|
||||||
#endif
|
#endif
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||||
|
@ -89,6 +89,7 @@
|
|||||||
*/
|
*/
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
|
||||||
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -87,6 +87,7 @@
|
|||||||
*/
|
*/
|
||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
|
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
|
||||||
|
@ -93,6 +93,7 @@
|
|||||||
#else
|
#else
|
||||||
#define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
|
#define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
|
||||||
#endif
|
#endif
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||||
|
@ -114,6 +114,7 @@
|
|||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#endif
|
#endif
|
||||||
#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
|
|
||||||
|
@ -127,6 +127,7 @@
|
|||||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||||
#endif
|
#endif
|
||||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
|
||||||
|
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
|
||||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||||
|
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user