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m5373evb: Update NAND driver to new API.

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Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Scott Wood 2008-08-13 17:53:48 -05:00
parent 1a23a197c8
commit f64cb652a8
1 changed files with 19 additions and 47 deletions
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66
board/freescale/m5373evb/nand.c
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@ -36,64 +36,39 @@ DECLARE_GLOBAL_DATA_PTR;
#include <linux/mtd/mtd.h> #include <linux/mtd/mtd.h>
#define SET_CLE 0x10 #define SET_CLE 0x10
#define CLR_CLE ~SET_CLE
#define SET_ALE 0x08 #define SET_ALE 0x08
#define CLR_ALE ~SET_ALE
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{ {
struct nand_chip *this = mtdinfo->priv; struct nand_chip *this = mtdinfo->priv;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
u32 nand_baseaddr = (u32) this->IO_ADDR_W; u32 nand_baseaddr = (u32) this->IO_ADDR_W;
switch (cmd) { if (ctrl & NAND_CTRL_CHANGE) {
case NAND_CTL_SETNCE: ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
case NAND_CTL_CLRNCE: IO_ADDR_W &= ~(SET_ALE | SE_CLE);
break;
case NAND_CTL_SETCLE: if (ctrl & NAND_CLE)
nand_baseaddr |= SET_CLE; IO_ADDR_W |= SET_CLE;
break; if (ctrl & NAND_ALE)
case NAND_CTL_CLRCLE: IO_ADDR_W |= SET_ALE;
nand_baseaddr &= CLR_CLE;
break; at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
case NAND_CTL_SETALE: this->IO_ADDR_W = (void *)IO_ADDR_W;
nand_baseaddr |= SET_ALE;
break;
case NAND_CTL_CLRALE:
nand_baseaddr |= CLR_ALE;
break;
case NAND_CTL_SETWP:
fbcs->csmr2 |= FBCS_CSMR_WP;
break;
case NAND_CTL_CLRWP:
fbcs->csmr2 &= ~FBCS_CSMR_WP;
break;
} }
this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
}
static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte) if (cmd != NAND_CMD_NONE)
{ writeb(cmd, this->IO_ADDR_W);
struct nand_chip *this = mtdinfo->priv;
*((volatile u8 *)(this->IO_ADDR_W)) = byte;
}
static u8 nand_read_byte(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
return (u8) (*((volatile u8 *)this->IO_ADDR_R));
}
static int nand_dev_ready(struct mtd_info *mtdinfo)
{
return 1;
} }
int board_nand_init(struct nand_chip *nand) int board_nand_init(struct nand_chip *nand)
{ {
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
*((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004;
fbcs->csmr2 &= ~FBCS_CSMR_WP;
/* set up pin configuration */ /* set up pin configuration */
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
@ -103,11 +78,8 @@ int board_nand_init(struct nand_chip *nand)
gpio->podr_timer = 0; gpio->podr_timer = 0;
nand->chip_delay = 50; nand->chip_delay = 50;
nand->eccmode = NAND_ECC_SOFT; nand->ecc.mode = NAND_ECC_SOFT;
nand->hwcontrol = nand_hwcontrol; nand->cmd_ctrl = nand_hwcontrol;
nand->read_byte = nand_read_byte;
nand->write_byte = nand_write_byte;
nand->dev_ready = nand_dev_ready;
return 0; return 0;
} }