powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL
e500v2 processor does not support 8K page size TLB entries. So create new TLB entry only during NAND SPL boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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@ -43,9 +43,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 1 */
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/* TLB 1 */
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/* *I*** - Covers boot page */
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/* *I*** - Covers boot page */
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SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
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SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_8K, 1),
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0, 0, BOOKE_PAGESZ_4K, 1),
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#ifdef CONFIG_SPL_NAND_MINIMAL
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SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 10, BOOKE_PAGESZ_4K, 1),
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#endif
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/* *I*G* - CCSRBAR (PA) */
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/* *I*G* - CCSRBAR (PA) */
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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@ -43,9 +43,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 1 */
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/* TLB 1 */
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/* *I*** - Covers boot page */
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/* *I*** - Covers boot page */
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SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
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SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_8K, 1),
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0, 0, BOOKE_PAGESZ_4K, 1),
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#ifdef CONFIG_SPL_NAND_MINIMAL
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SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 10, BOOKE_PAGESZ_4K, 1),
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#endif
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/* *I*G* - CCSRBAR (PA) */
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/* *I*G* - CCSRBAR (PA) */
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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@ -43,9 +43,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 1 */
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/* TLB 1 */
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/* *I*** - Covers boot page */
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/* *I*** - Covers boot page */
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SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_4K, 1),
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#ifdef CONFIG_SPL_NAND_MINIMAL
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SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
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SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_8K, 1),
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0, 10, BOOKE_PAGESZ_4K, 1),
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#endif
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/* *I*G* - CCSRBAR */
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/* *I*G* - CCSRBAR */
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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