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https://github.com/brain-hackers/u-boot-brain
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clk: mediatek: add set_clr_upd mux type flow
Add new set_clr_upd mux type and related operation to mtk common clock driver to support mt8512
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parent
c196110777
commit
f62168d3c3
@ -67,12 +67,23 @@ static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent,
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if (++index == mux->num_parents)
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return -EINVAL;
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if (mux->flags & CLK_MUX_SETCLR_UPD) {
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val = (mux->mux_mask << mux->mux_shift);
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writel(val, base + mux->mux_clr_reg);
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val = (index << mux->mux_shift);
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writel(val, base + mux->mux_set_reg);
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if (mux->upd_shift >= 0)
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writel(BIT(mux->upd_shift), base + mux->upd_reg);
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} else {
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/* switch mux to a select parent */
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val = readl(base + mux->mux_reg);
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val &= ~(mux->mux_mask << mux->mux_shift);
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val |= index << mux->mux_shift;
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writel(val, base + mux->mux_reg);
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}
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return 0;
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}
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@ -332,9 +343,14 @@ static int mtk_topckgen_enable(struct clk *clk)
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return 0;
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/* enable clock gate */
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if (mux->flags & CLK_MUX_SETCLR_UPD) {
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val = BIT(mux->gate_shift);
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writel(val, priv->base + mux->mux_clr_reg);
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} else {
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val = readl(priv->base + mux->gate_reg);
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val &= ~BIT(mux->gate_shift);
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writel(val, priv->base + mux->gate_reg);
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}
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if (mux->flags & CLK_DOMAIN_SCPSYS) {
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/* enable scpsys clock off control */
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@ -360,9 +376,14 @@ static int mtk_topckgen_disable(struct clk *clk)
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return 0;
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/* disable clock gate */
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if (mux->flags & CLK_MUX_SETCLR_UPD) {
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val = BIT(mux->gate_shift);
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writel(val, priv->base + mux->mux_set_reg);
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} else {
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val = readl(priv->base + mux->gate_reg);
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val |= BIT(mux->gate_shift);
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writel(val, priv->base + mux->gate_reg);
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}
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return 0;
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}
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@ -12,6 +12,7 @@
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#define HAVE_RST_BAR BIT(0)
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#define CLK_DOMAIN_SCPSYS BIT(0)
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#define CLK_MUX_SETCLR_UPD BIT(1)
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#define CLK_GATE_SETCLR BIT(0)
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#define CLK_GATE_SETCLR_INV BIT(1)
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@ -102,9 +103,13 @@ struct mtk_composite {
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const int id;
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const int *parent;
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u32 mux_reg;
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u32 mux_set_reg;
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u32 mux_clr_reg;
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u32 upd_reg;
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u32 gate_reg;
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u32 mux_mask;
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signed char mux_shift;
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signed char upd_shift;
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signed char gate_shift;
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signed char num_parents;
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u16 flags;
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@ -137,6 +142,24 @@ struct mtk_composite {
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.flags = 0, \
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}
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#define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\
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_mux_clr_ofs, _shift, _width, _gate, \
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_upd_ofs, _upd, _flags) { \
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.id = _id, \
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.mux_reg = _mux_ofs, \
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.mux_set_reg = _mux_set_ofs, \
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.mux_clr_reg = _mux_clr_ofs, \
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.upd_reg = _upd_ofs, \
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.upd_shift = _upd, \
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.mux_shift = _shift, \
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.mux_mask = BIT(_width) - 1, \
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.gate_reg = _mux_ofs, \
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.gate_shift = _gate, \
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.parent = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = _flags, \
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}
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struct mtk_gate_regs {
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u32 sta_ofs;
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u32 clr_ofs;
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