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ARM: zynq: slcr: Dont modify the reserved bits
Set only the 0-3 bits of the FPGA_RST_CTRL register as other bits should not be set to 1. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -132,7 +132,7 @@ void zynq_slcr_devcfg_disable(void)
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zynq_slcr_unlock();
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zynq_slcr_unlock();
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/* Disable AXI interface by asserting FPGA resets */
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/* Disable AXI interface by asserting FPGA resets */
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writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
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writel(0xF, &slcr_base->fpga_rst_ctrl);
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/* Set Level Shifters DT618760 */
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/* Set Level Shifters DT618760 */
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writel(0xA, &slcr_base->lvl_shftr_en);
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writel(0xA, &slcr_base->lvl_shftr_en);
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