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https://github.com/brain-hackers/u-boot-brain
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sunxi_nand_spl: Parametrize lowlevel read functions
Parametrize the lowlevel nand_read_page function, instead of directly using the CONFIG_foo settings for page-size, etc. there and add a few wrappers / helper functions for calling it. This is a preparation patch for adding auto-detecting of the nand parameters like the BROM does. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
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0a247554c2
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@ -179,8 +179,8 @@ void nand_init(void)
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}
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}
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}
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}
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static void nand_read_page(unsigned int real_addr, dma_addr_t dst,
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static int nand_read_page(int page_size, int ecc_strength, int ecc_page_size,
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int syndrome, uint32_t *ecc_errors)
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int addr_cycles, uint32_t real_addr, dma_addr_t dst, int syndrome)
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{
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{
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uint32_t val;
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uint32_t val;
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int i, ecc_off = 0;
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int i, ecc_off = 0;
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@ -188,28 +188,26 @@ static void nand_read_page(unsigned int real_addr, dma_addr_t dst,
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uint16_t rand_seed;
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uint16_t rand_seed;
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uint32_t page;
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uint32_t page;
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uint16_t column;
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uint16_t column;
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uint32_t oob_offset;
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static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
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static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
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for (i = 0; i < ARRAY_SIZE(strengths); i++) {
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for (i = 0; i < ARRAY_SIZE(strengths); i++) {
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if (CONFIG_NAND_SUNXI_SPL_ECC_STRENGTH == strengths[i]) {
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if (ecc_strength == strengths[i]) {
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ecc_mode = i;
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ecc_mode = i;
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break;
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break;
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}
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}
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}
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}
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/* HW ECC always request ECC bytes for 1024 bytes blocks */
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/* HW ECC always request ECC bytes for 1024 bytes blocks */
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ecc_off = DIV_ROUND_UP(CONFIG_NAND_SUNXI_SPL_ECC_STRENGTH * fls(8 * 1024), 8);
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ecc_off = DIV_ROUND_UP(ecc_strength * fls(8 * 1024), 8);
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/* HW ECC always work with even numbers of ECC bytes */
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/* HW ECC always work with even numbers of ECC bytes */
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ecc_off += (ecc_off & 1);
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ecc_off += (ecc_off & 1);
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ecc_off += 4; /* prepad */
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ecc_off += 4; /* prepad */
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page = real_addr / CONFIG_NAND_SUNXI_SPL_PAGE_SIZE;
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page = real_addr / page_size;
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column = real_addr % CONFIG_NAND_SUNXI_SPL_PAGE_SIZE;
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column = real_addr % page_size;
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if (syndrome)
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if (syndrome)
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column += (column / CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
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column += (column / ecc_page_size) * ecc_off;
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* ecc_off;
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/* clear ecc status */
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/* clear ecc status */
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writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
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writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
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@ -227,16 +225,11 @@ static void nand_read_page(unsigned int real_addr, dma_addr_t dst,
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val = readl(SUNXI_NFC_BASE + NFC_CTL);
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val = readl(SUNXI_NFC_BASE + NFC_CTL);
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writel(val | NFC_CTL_RAM_METHOD, SUNXI_NFC_BASE + NFC_CTL);
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writel(val | NFC_CTL_RAM_METHOD, SUNXI_NFC_BASE + NFC_CTL);
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if (!syndrome) {
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if (!syndrome)
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oob_offset = CONFIG_NAND_SUNXI_SPL_PAGE_SIZE
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writel(page_size + (column / ecc_page_size) * ecc_off,
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+ (column / CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
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SUNXI_NFC_BASE + NFC_SPARE_AREA);
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* ecc_off;
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writel(oob_offset, SUNXI_NFC_BASE + NFC_SPARE_AREA);
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}
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flush_dcache_range(dst,
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flush_dcache_range(dst, ALIGN(dst + ecc_page_size, ARCH_DMA_MINALIGN));
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ALIGN(dst + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
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ARCH_DMA_MINALIGN));
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/* SUNXI_DMA */
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/* SUNXI_DMA */
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writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
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writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
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@ -248,7 +241,7 @@ static void nand_read_page(unsigned int real_addr, dma_addr_t dst,
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writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC
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writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC
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| SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE,
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| SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE,
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SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0);
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SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0);
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writel(CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
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writel(ecc_page_size,
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SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0); /* 1kB */
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SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0); /* 1kB */
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writel(SUNXI_DMA_DDMA_CFG_REG_LOADING
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writel(SUNXI_DMA_DDMA_CFG_REG_LOADING
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| SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32
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| SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32
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@ -267,47 +260,64 @@ static void nand_read_page(unsigned int real_addr, dma_addr_t dst,
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SUNXI_NFC_BASE + NFC_ADDR_LOW);
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SUNXI_NFC_BASE + NFC_ADDR_LOW);
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writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
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writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
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writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_DATA_TRANS |
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writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_DATA_TRANS |
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NFC_PAGE_CMD | NFC_WAIT_FLAG | (4 << NFC_ADDR_NUM_OFFSET) |
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NFC_PAGE_CMD | NFC_WAIT_FLAG |
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((addr_cycles - 1) << NFC_ADDR_NUM_OFFSET) |
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NFC_SEND_ADR | NFC_DATA_SWAP_METHOD | (syndrome ? NFC_SEQ : 0),
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NFC_SEND_ADR | NFC_DATA_SWAP_METHOD | (syndrome ? NFC_SEQ : 0),
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SUNXI_NFC_BASE + NFC_CMD);
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SUNXI_NFC_BASE + NFC_CMD);
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if (!check_value(SUNXI_NFC_BASE + NFC_ST, (1 << 2),
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if (!check_value(SUNXI_NFC_BASE + NFC_ST, (1 << 2),
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MAX_RETRIES)) {
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MAX_RETRIES)) {
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printf("Error while initializing dma interrupt\n");
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printf("Error while initializing dma interrupt\n");
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return;
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return -1;
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}
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}
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if (!check_value_negated(SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0,
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if (!check_value_negated(SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0,
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SUNXI_DMA_DDMA_CFG_REG_LOADING, MAX_RETRIES)) {
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SUNXI_DMA_DDMA_CFG_REG_LOADING, MAX_RETRIES)) {
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printf("Error while waiting for dma transfer to finish\n");
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printf("Error while waiting for dma transfer to finish\n");
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return;
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return -1;
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}
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}
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invalidate_dcache_range(dst,
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invalidate_dcache_range(dst,
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ALIGN(dst + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
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ALIGN(dst + ecc_page_size, ARCH_DMA_MINALIGN));
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ARCH_DMA_MINALIGN));
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if (readl(SUNXI_NFC_BASE + NFC_ECC_ST))
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if (readl(SUNXI_NFC_BASE + NFC_ECC_ST))
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(*ecc_errors)++;
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return -1;
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return 0;
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}
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static int nand_read_ecc(int page_size, int ecc_strength, int ecc_page_size,
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int addr_cycles, uint32_t offs, uint32_t size, void *dest, int syndrome)
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{
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void *end = dest + size;
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clrsetbits_le32(SUNXI_NFC_BASE + NFC_CTL, NFC_CTL_PAGE_SIZE_MASK,
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NFC_CTL_PAGE_SIZE(page_size));
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for ( ;dest < end; dest += ecc_page_size, offs += ecc_page_size) {
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if (nand_read_page(page_size, ecc_strength, ecc_page_size,
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addr_cycles, offs, (dma_addr_t)dest,
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syndrome))
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return -1;
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}
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return 0;
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}
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static int nand_read_buffer(uint32_t offs, unsigned int size, void *dest,
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int syndrome)
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{
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return nand_read_ecc(CONFIG_NAND_SUNXI_SPL_PAGE_SIZE,
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CONFIG_NAND_SUNXI_SPL_ECC_STRENGTH,
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CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
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5, offs, size, dest, syndrome);
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}
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}
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int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
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int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
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{
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{
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void *current_dest;
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int syndrome = offs < CONFIG_NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END;
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uint32_t ecc_errors = 0;
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clrsetbits_le32(SUNXI_NFC_BASE + NFC_CTL, NFC_CTL_PAGE_SIZE_MASK,
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return nand_read_buffer(offs, size, dest, syndrome);
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NFC_CTL_PAGE_SIZE(CONFIG_NAND_SUNXI_SPL_PAGE_SIZE));
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for (current_dest = dest;
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current_dest < (dest + size);
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current_dest += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE) {
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nand_read_page(offs, (dma_addr_t)current_dest,
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offs < CONFIG_NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END,
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&ecc_errors);
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offs += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
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}
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return ecc_errors ? -1 : 0;
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}
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}
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void nand_deselect(void)
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void nand_deselect(void)
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