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x86: apl: Support set_hide() in p2sb driver

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Add support for this new method in the driver and in the fsp-s setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
This commit is contained in:
Simon Glass 2020-07-07 21:32:31 -06:00 committed by Bin Meng
parent 6d349e2e43
commit f549d9bbde
2 changed files with 42 additions and 15 deletions
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26
arch/x86/cpu/apollolake/fsp_s.c
View File

@ -12,6 +12,7 @@
#include <irq.h>
#include <log.h>
#include <malloc.h>
#include <p2sb.h>
#include <acpi/acpi_s3.h>
#include <asm/intel_pinctrl.h>
#include <asm/io.h>
@ -21,10 +22,11 @@
#include <asm/pci.h>
#include <asm/arch/cpu.h>
#include <asm/arch/systemagent.h>
#include <asm/arch/fsp_bindings.h>
#include <asm/arch/fsp/fsp_configs.h>
#include <asm/arch/fsp/fsp_s_upd.h>
#include <dm/uclass-internal.h>
#include <linux/bitops.h>
#include <asm/arch/fsp_bindings.h>
#define PCH_P2SB_E0 0xe0
#define HIDE_BIT BIT(0)
@ -59,12 +61,6 @@ int fsps_update_config(struct udevice *dev, ulong rom_offset,
return fsp_s_update_config_from_dtb(node, cfg);
}
static void p2sb_set_hide_bit(pci_dev_t dev, int hide)
{
pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
hide ? HIDE_BIT : 0, PCI_SIZE_8);
}
/* Configure package power limits */
static int set_power_limits(struct udevice *dev)
{
@ -137,15 +133,15 @@ static int set_power_limits(struct udevice *dev)
int p2sb_unhide(void)
{
pci_dev_t dev = PCI_BDF(0, 0xd, 0);
ulong val;
struct udevice *dev;
int ret;
p2sb_set_hide_bit(dev, 0);
pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16);
if (val != PCI_VENDOR_ID_INTEL)
return log_msg_ret("p2sb unhide", -EIO);
ret = uclass_find_first_device(UCLASS_P2SB, &dev);
if (ret)
return log_msg_ret("p2sb", ret);
ret = p2sb_set_hide(dev, false);
if (ret)
return log_msg_ret("hide", ret);
return 0;
}

31
arch/x86/cpu/intel_common/p2sb.c
View File

@ -16,6 +16,9 @@
#include <asm/pci.h>
#include <linux/bitops.h>
#define PCH_P2SB_E0 0xe0
#define HIDE_BIT BIT(0)
struct p2sb_platdata {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_p2sb dtplat;
@ -127,6 +130,29 @@ static int p2sb_probe(struct udevice *dev)
return 0;
}
static void p2sb_set_hide_bit(struct udevice *dev, bool hide)
{
dm_pci_clrset_config8(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
hide ? HIDE_BIT : 0);
}
static int intel_p2sb_set_hide(struct udevice *dev, bool hide)
{
u16 vendor;
if (!CONFIG_IS_ENABLED(PCI))
return -EPERM;
p2sb_set_hide_bit(dev, hide);
dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
if (hide && vendor != 0xffff)
return log_msg_ret("hide", -EEXIST);
else if (!hide && vendor != PCI_VENDOR_ID_INTEL)
return log_msg_ret("unhide", -ENOMEDIUM);
return 0;
}
static int p2sb_child_post_bind(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
@ -143,6 +169,10 @@ static int p2sb_child_post_bind(struct udevice *dev)
return 0;
}
struct p2sb_ops p2sb_ops = {
.set_hide = intel_p2sb_set_hide,
};
static const struct udevice_id p2sb_ids[] = {
{ .compatible = "intel,p2sb" },
{ }
@ -153,6 +183,7 @@ U_BOOT_DRIVER(p2sb_drv) = {
.id = UCLASS_P2SB,
.of_match = p2sb_ids,
.probe = p2sb_probe,
.ops = &p2sb_ops,
.ofdata_to_platdata = p2sb_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
.per_child_platdata_auto_alloc_size =