diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 388e4c0f0d..1b39c4c0c6 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -28,6 +28,7 @@ config TARGET_MALTA
 	select SUPPORTS_CPU_MIPS32_R1
 	select SUPPORTS_CPU_MIPS32_R2
 	select SWAP_IO_SPACE
+	select MIPS_L1_CACHE_SHIFT_6
 
 config TARGET_VCT
 	bool "Support vct"
@@ -196,6 +197,26 @@ config SWAP_IO_SPACE
 config SYS_MIPS_CACHE_INIT_RAM_LOAD
 	bool
 
+config MIPS_L1_CACHE_SHIFT_4
+	bool
+
+config MIPS_L1_CACHE_SHIFT_5
+	bool
+
+config MIPS_L1_CACHE_SHIFT_6
+	bool
+
+config MIPS_L1_CACHE_SHIFT_7
+	bool
+
+config MIPS_L1_CACHE_SHIFT
+	int
+	default "7" if MIPS_L1_CACHE_SHIFT_7
+	default "6" if MIPS_L1_CACHE_SHIFT_6
+	default "5" if MIPS_L1_CACHE_SHIFT_5
+	default "4" if MIPS_L1_CACHE_SHIFT_4
+	default "5"
+
 endif
 
 endmenu
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 0dfb54ef4d..806bd26ba9 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -7,15 +7,9 @@
 #ifndef __MIPS_CACHE_H__
 #define __MIPS_CACHE_H__
 
-/*
- * The maximum L1 data cache line size on MIPS seems to be 128 bytes.  We use
- * that as a default for aligning DMA buffers unless the board config has
- * specified another cache line size.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN	128
-#endif
+#define L1_CACHE_SHIFT		CONFIG_MIPS_L1_CACHE_SHIFT
+#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
+
+#define ARCH_DMA_MINALIGN	(L1_CACHE_BYTES)
 
 #endif /* __MIPS_CACHE_H__ */