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ARM: socfpga: Cleaning up and ensuring consistent format messages in driver
Ensure all the debug messages are always prefix with "FPGA: " and comment beginning with uppercase letter. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
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@ -94,7 +94,7 @@ int fpgamgr_wait_early_user_mode(void)
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i++;
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}
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debug("Additional %i sync word needed\n", i);
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debug("FPGA: Additional %i sync word needed\n", i);
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/* restoring original CDRATIO */
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fpgamgr_set_cd_ratio(cd_ratio);
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@ -172,9 +172,10 @@ static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
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compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
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compress = !compress;
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debug("header word %d = %08x\n", 69, rbf_data[69]);
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debug("header word %d = %08x\n", 229, rbf_data[229]);
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debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
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debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
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debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
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debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
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compress);
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/*
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* from the register map description of cdratio in imgcfg_ctrl_02:
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@ -455,10 +456,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
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{
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int status;
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/* disable all signals from hps peripheral controller to fpga */
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/* Disable all signals from hps peripheral controller to fpga */
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writel(0, &system_manager_base->fpgaintf_en_global);
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/* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
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/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
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socfpga_bridges_reset();
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/* Initialize the FPGA Manager */
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