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ARM: tegra: error check Tegra210 XUSB padctl waits

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Add code to detect timeouts when waiting for HW events such as PLL
lock done. Any errors are logged and trigger an error return code.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren 2015-10-23 10:50:53 -06:00 committed by Tom Warren
parent 4e4b5574fb
commit f35cb12511
1 changed files with 20 additions and 5 deletions
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25
arch/arm/mach-tegra/tegra210/xusb-padctl.c
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@ -279,7 +279,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
break;
}
if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) {
debug(" timeout\n");
return -ETIMEDOUT;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
@ -295,7 +298,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
break;
}
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) {
debug(" timeout\n");
return -ETIMEDOUT;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
@ -310,7 +316,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
break;
}
if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) {
debug(" timeout\n");
return -ETIMEDOUT;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
@ -326,7 +335,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
break;
}
if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) {
debug(" timeout\n");
return -ETIMEDOUT;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
@ -341,7 +353,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
break;
}
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) {
debug(" timeout\n");
return -ETIMEDOUT;
}
debug(" done\n");
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);