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u-boot-brain
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Merge tag 'rockchip-for-v2019.07-rc1' of git://git.denx.de/u-boot-rockchip 

Improvements and new features:
- split more rockchip pinctrl_core feature into per SoC
- enable TPL for evb-rk3399 board
- enable TPL/SPL for evb-px5 board
- enable TPL and OP-TEE support for evb-rk3229
- update fix in arm common assembly start code for rockchip header file
- update default SPL_FIT_GENERATOR for rockchip
- rk3399 boards update to use '-u-boot.dtsi'
- add new rk3399 boards: Nanopi M4, Nanopc T4
- enable sound for chromebook_minnie
This commit is contained in:
Tom Rini 2019-05-09 07:12:51 -04:00
parent 062aceb8bf c661c059b9
commit f30f268a07
104 changed files with 3115 additions and 673 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Kconfig
View File

@ -435,6 +435,7 @@ config SPL_FIT_GENERATOR
string ".its file generator script for U-Boot FIT image"
depends on SPL_FIT
default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP
help
Specifies a (platform specific) script file to generate the FIT
source file used to build the U-Boot FIT image file. This gets

1
arch/Kconfig
View File

@ -160,6 +160,7 @@ config X86
imply DM_USB
imply DM_VIDEO
imply SYSRESET
imply SPL_SYSRESET
imply SYSRESET_X86
imply USB_ETHER_ASIX
imply USB_ETHER_SMSC95XX

30
arch/arm/Kconfig
View File

@ -338,6 +338,17 @@ config SPL_SYS_THUMB_BUILD
density. For ARM architectures that support Thumb2 this flag will
result in Thumb2 code generated by GCC.
config TPL_SYS_THUMB_BUILD
bool "Build TPL using the Thumb instruction set"
default y if SYS_THUMB_BUILD
depends on TPL && !ARM64
help
Use this flag to build SPL using the Thumb instruction set for
ARM architectures. Thumb instruction set provides better code
density. For ARM architectures that support Thumb2 this flag will
result in Thumb2 code generated by GCC.
config SYS_L2CACHE_OFF
bool "L2cache off"
help
@ -373,6 +384,15 @@ config SPL_USE_ARCH_MEMCPY
Such implementation may be faster under some conditions
but may increase the binary size.
config TPL_USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy for TPL"
default y if USE_ARCH_MEMCPY
depends on !ARM64
help
Enable the generation of an optimized version of memcpy.
Such implementation may be faster under some conditions
but may increase the binary size.
config USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset"
default y
@ -391,6 +411,15 @@ config SPL_USE_ARCH_MEMSET
Such implementation may be faster under some conditions
but may increase the binary size.
config TPL_USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset for TPL"
default y if USE_ARCH_MEMSET
depends on !ARM64
help
Enable the generation of an optimized version of memset.
Such implementation may be faster under some conditions
but may increase the binary size.
config ARM64_SUPPORT_AARCH32
bool "ARM64 system support AArch32 execution state"
default y if ARM64 && !TARGET_THUNDERX_88XX
@ -1407,6 +1436,7 @@ config ARCH_STM32MP
select SYSCON
select SYSRESET
select SYS_THUMB_BUILD
imply SPL_SYSRESET
imply CMD_DM
imply CMD_POWEROFF
imply ENV_VARS_UBOOT_RUNTIME_CONFIG

4
arch/arm/cpu/armv8/start.S
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@ -26,11 +26,7 @@ _start:
* order to boot, allow them to set that in their boot0.h file and then
* use it here.
*/
#ifdef CONFIG_ARCH_ROCKCHIP
#include <asm/arch-rockchip/boot0.h>
#else
#include <asm/arch/boot0.h>
#endif
#else
b reset
#endif

37
arch/arm/dts/Makefile
View File

@ -65,16 +65,23 @@ dtb-$(CONFIG_KIRKWOOD) += \
dtb-$(CONFIG_ARCH_OWL) += \
bubblegum_96.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3036-sdk.dtb \
rk3128-evb.dtb \
rk3188-radxarock.dtb \
rk3229-evb.dtb \
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
rk3036-sdk.dtb
dtb-$(CONFIG_ROCKCHIP_RK3128) += \
rk3128-evb.dtb
dtb-$(CONFIG_ROCKCHIP_RK3188) += \
rk3188-radxarock.dtb
dtb-$(CONFIG_ROCKCHIP_RK322X) += \
rk3229-evb.dtb
dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-evb.dtb \
rk3288-fennec.dtb \
rk3288-firefly.dtb \
rk3288-miqi.dtb \
rk3399-orangepi.dtb \
rk3288-phycore-rdk.dtb \
rk3288-popmetal.dtb \
rk3288-rock2-square.dtb \
@ -83,22 +90,34 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb \
rk3328-evb.dtb \
rk3399-ficus.dtb \
rk3288-vyasa.dtb
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-lion.dtb \
rk3368-sheep.dtb \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-evb.dtb \
rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
rk3399-rock960.dtb \
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb
dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-odroidc2.dtb \

1
arch/arm/dts/rk3229-evb.dts
View File

@ -82,6 +82,7 @@
};
&uart2 {
u-boot,dm-pre-reloc;
status = "okay";
};

12
arch/arm/dts/rk3288-veyron-minnie.dts
View File

@ -85,6 +85,18 @@
regulator-boot-on;
vin-supply = <&vcc18_wl>;
};
sound {
compatible = "rockchip,audio-max98090-jerry";
cpu {
sound-dai = <&i2s 0>;
};
codec {
sound-dai = <&max98090 0>;
};
};
};
&backlight {

36
arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
View File

@ -2,6 +2,28 @@
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
/ {
chosen {
u-boot,spl-boot-order = &emmc;
tick-timer = "/timer@ff810000";
};
};
&dmc {
u-boot,dm-pre-reloc;
/*
* PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct
* See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
* details on the 'rockchip,memory-schedule' property and how it
* affects the physical-address to device-address mapping.
*/
rockchip,memory-schedule = <DMC_MSCH_CBRD>;
rockchip,ddr-frequency = <800000000>;
rockchip,ddr-speed-bin = <DDR3_1600K>;
status = "okay";
};
&pinctrl {
u-boot,dm-pre-reloc;
@ -20,6 +42,10 @@
u-boot,dm-pre-reloc;
};
&sgrf {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
@ -31,3 +57,13 @@
&uart4 {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&timer0 {
u-boot,dm-pre-reloc;
clock-frequency = <24000000>;
status = "okay";
};

7
arch/arm/dts/rk3399-evb-u-boot.dtsi Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"

1
arch/arm/dts/rk3399-evb.dts
View File

@ -7,7 +7,6 @@
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
/ {
model = "Rockchip RK3399 Evaluation Board";

6
arch/arm/dts/rk3399-ficus-u-boot.dtsi Normal file
View File

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-sdram-ddr3-1600.dtsi"

1
arch/arm/dts/rk3399-ficus.dts
View File

@ -8,7 +8,6 @@
/dts-v1/;
#include "rk3399-rock960.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"
/ {
model = "96boards RK3399 Ficus";

7
arch/arm/dts/rk3399-firefly-u-boot.dtsi Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"

1
arch/arm/dts/rk3399-firefly.dts
View File

@ -7,7 +7,6 @@
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"
/ {
model = "Firefly-RK3399 Board";

7
arch/arm/dts/rk3399-gru-bob-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-gru-u-boot.dtsi"
#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"

1
arch/arm/dts/rk3399-gru-bob.dts
View File

@ -7,7 +7,6 @@
/dts-v1/;
#include "rk3399-gru-chromebook.dtsi"
#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
/ {
model = "Google Bob";

6
arch/arm/dts/rk3399-gru-u-boot.dtsi Normal file
View File

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-u-boot.dtsi"

1
arch/arm/dts/rk3399-gru.dtsi
View File

@ -545,7 +545,6 @@ ap_i2c_audio: &i2c8 {
&spi1 {
status = "okay";
u-boot,dm-pre-reloc;
pinctrl-names = "default", "sleep";
pinctrl-1 = <&spi1_sleep>;

7
arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-nanopi4-u-boot.dtsi"
#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"

91
arch/arm/dts/rk3399-nanopc-t4.dts Normal file
View File

@ -0,0 +1,91 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* FriendlyElec NanoPC-T4 board device tree source
*
* Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*
* Copyright (c) 2018 Collabora Ltd.
*/
/dts-v1/;
#include "rk3399-nanopi4.dtsi"
/ {
model = "FriendlyElec NanoPC-T4";
compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
vcc12v0_sys: vcc12v0-sys {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <12000000>;
regulator-min-microvolt = <12000000>;
regulator-name = "vcc12v0_sys";
};
vcc5v0_host0: vcc5v0-host0 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc5v0_host0";
vin-supply = <&vcc5v0_sys>;
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <18000>;
};
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_rx>;
};
};
&pinctrl {
ir {
ir_rx: ir-rx {
/* external pullup to VCC3V3_SYS, despite being 1.8V :/ */
rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
};
};
};
&sdhci {
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
&u2phy0_host {
phy-supply = <&vcc5v0_host0>;
};
&u2phy1_host {
phy-supply = <&vcc5v0_host0>;
};
&vcc5v0_sys {
vin-supply = <&vcc12v0_sys>;
};
&vcc3v3_sys {
vin-supply = <&vcc12v0_sys>;
};
&vbus_typec {
enable-active-high;
gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
};

7
arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-nanopi4-u-boot.dtsi"
#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"

66
arch/arm/dts/rk3399-nanopi-m4.dts Normal file
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@ -0,0 +1,66 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* FriendlyElec NanoPi M4 board device tree source
*
* Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*
* Copyright (c) 2018 Collabora Ltd.
* Copyright (c) 2019 Arm Ltd.
*/
/dts-v1/;
#include "rk3399-nanopi4.dtsi"
/ {
model = "FriendlyElec NanoPi M4";
compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
vdd_5v: vdd-5v {
compatible = "regulator-fixed";
regulator-name = "vdd_5v";
regulator-always-on;
regulator-boot-on;
};
vcc5v0_core: vcc5v0-core {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_core";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd_5v>;
};
vcc5v0_usb1: vcc5v0-usb1 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb1";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_usb2: vcc5v0-usb2 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb2";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
};
&vcc3v3_sys {
vin-supply = <&vcc5v0_core>;
};
&u2phy0_host {
phy-supply = <&vcc5v0_usb1>;
};
&u2phy1_host {
phy-supply = <&vcc5v0_usb2>;
};
&vbus_typec {
regulator-always-on;
vin-supply = <&vdd_5v>;
};

10
arch/arm/dts/rk3399-nanopi4-u-boot.dtsi Normal file
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@ -0,0 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-u-boot.dtsi"
&sdmmc {
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
};

703
arch/arm/dts/rk3399-nanopi4.dtsi Normal file
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@ -0,0 +1,703 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* RK3399-based FriendlyElec boards device tree source
*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*
* Copyright (c) 2018 Collabora Ltd.
* Copyright (c) 2019 Arm Ltd.
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
chosen {
stdout-path = "serial2:1500000n8";
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_sys";
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vcc5v0_sys";
vin-supply = <&vdd_5v>;
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_s3";
vin-supply = <&vcc_1v8>;
};
vcc3v0_sd: vcc3v0-sd {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_pwr_h>;
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc3v0_sd";
vin-supply = <&vcc3v3_sys>;
};
vbus_typec: vbus-typec {
compatible = "regulator-fixed";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vbus_typec";
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&power_key>;
power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
linux,code = <KEY_POWER>;
wakeup-source;
};
};
leds: gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_gpio>;
status {
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
label = "status_led";
linux,default-trigger = "heartbeat";
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_reg_on_h>;
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clock-parents = <&clkin_gmac>;
assigned-clocks = <&cru SCLK_RMII_SRC>;
clock_in_out = "input";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-supply = <&vcc3v3_s3>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c7>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <160>;
i2c-scl-falling-time-ns = <30>;
status = "okay";
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&cpu_b_sleep>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd_cpu_b";
regulator-ramp-delay = <1000>;
vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&gpu_sleep>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd_gpu";
regulator-ramp-delay = <1000>;
vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
clock-output-names = "xin32k", "rtc_clko_wifi";
#clock-cells = <1>;
interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
vcc10-supply = <&vcc3v3_sys>;
vcc11-supply = <&vcc3v3_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_3v0>;
regulators {
vdd_center: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-name = "vdd_center";
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-name = "vdd_cpu_l";
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v8_cam: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_cam";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v0_touch: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc3v0_touch";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmupll: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_pmupll";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_sdio: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <3000000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sdio";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcca3v0_codec: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcca3v0_codec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc_1v5";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcca1v8_codec: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_codec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_3v0";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_s3: SWITCH_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc3v3_s3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&i2c1 {
clock-frequency = <200000>;
i2c-scl-rising-time-ns = <150>;
i2c-scl-falling-time-ns = <30>;
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <160>;
i2c-scl-falling-time-ns = <30>;
status = "okay";
fusb0: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
vbus-supply = <&vbus_typec>;
};
};
&i2c7 {
status = "okay";
};
&io_domains {
bt656-supply = <&vcc_1v8>;
audio-supply = <&vcca1v8_codec>;
sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>;
status = "okay";
};
&pcie_phy {
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
assigned-clock-rates = <100000000>;
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
max-link-speed = <2>;
num-lanes = <4>;
status = "okay";
};
&pinctrl {
fusb30x {
fusb0_int: fusb0-int {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
gpio-leds {
leds_gpio: leds-gpio {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
cpu_b_sleep: cpu-b-sleep {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
gpu_sleep: gpu-sleep {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
rockchip-key {
power_key: power-key {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio {
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_reg_on_h: bt-reg-on-h {
/* external pullup to VCC1V8_PMUPLL */
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_reg_on_h: wifi-reg_on-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdmmc {
sdmmc0_det_l: sdmmc0-det-l {
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
sdmmc0_pwr_h: sdmmc0-pwr-h {
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0>;
status = "okay";
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm2 {
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin_pull_down>;
status = "okay";
};
&saradc {
vref-supply = <&vcca1v8_s3>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
status = "okay";
};
&sdio0 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v0_sd>;
vqmmc-supply = <&vcc_sdio>;
status = "okay";
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
/* tshut polarity 0:LOW 1:HIGH */
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
};
&u2phy0_host {
status = "okay";
};
&u2phy0_otg {
status = "okay";
};
&u2phy1 {
status = "okay";
};
&u2phy1_host {
status = "okay";
};
&u2phy1_otg {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
max-speed = <4000000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
};
};
&uart2 {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
};
&usbdrd_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

1
arch/arm/dts/rk3399-puma-ddr1600.dts
View File

@ -6,5 +6,6 @@
/dts-v1/;
#include "rk3399-puma.dtsi"
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"

2
arch/arm/dts/rk3399-puma.dtsi
View File

@ -647,8 +647,6 @@
&spi1 {
u-boot,dm-pre-reloc;
status = "okay";
#address-cells = <1>;

6
arch/arm/dts/rk3399-rock960-u-boot.dtsi Normal file
View File

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-sdram-lpddr3-2GB-1600.dtsi"

1
arch/arm/dts/rk3399-rock960.dts
View File

@ -5,7 +5,6 @@
/dts-v1/;
#include "rk3399-rock960.dtsi"
#include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
/ {
model = "96boards Rock960";

4
arch/arm/dts/rk3399-u-boot.dtsi
View File

@ -6,3 +6,7 @@
&sdmmc {
u-boot,dm-pre-reloc;
};
&spi1 {
u-boot,dm-pre-reloc;
};

5
arch/arm/dts/rk3399.dtsi
View File

@ -2495,6 +2495,11 @@
rockchip,pins =
<1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
};
pwm2_pin_pull_down: pwm2-pin-pull-down {
rockchip,pins =
<1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;
};
};
pwm3a {

11
arch/arm/include/asm/arch-rk3036/boot0.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

11
arch/arm/include/asm/arch-rk3036/gpio.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

11
arch/arm/include/asm/arch-rk3128/boot0.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

11
arch/arm/include/asm/arch-rk3128/gpio.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

11
arch/arm/include/asm/arch-rk3188/boot0.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

11
arch/arm/include/asm/arch-rk3188/gpio.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

11
arch/arm/include/asm/arch-rk322x/boot0.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

11
arch/arm/include/asm/arch-rk322x/gpio.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

11
arch/arm/include/asm/arch-rk3288/boot0.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

11
arch/arm/include/asm/arch-rk3288/gpio.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

11
arch/arm/include/asm/arch-rk3328/boot0.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

11
arch/arm/include/asm/arch-rk3328/gpio.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

11
arch/arm/include/asm/arch-rk3368/boot0.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

11
arch/arm/include/asm/arch-rk3368/gpio.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

11
arch/arm/include/asm/arch-rk3399/boot0.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

11
arch/arm/include/asm/arch-rk3399/gpio.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

3
arch/arm/include/asm/arch-rockchip/boot0.h
View File

@ -54,6 +54,7 @@ _start:
ARM_VECTORS
#endif
#if defined(CONFIG_SPL_BUILD) && (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0)
#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \
(CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0)
.space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */
#endif

11
arch/arm/include/asm/arch-rv1108/boot0.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

11
arch/arm/include/asm/arch-rv1108/gpio.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

4
arch/arm/lib/crt0.S
View File

@ -67,7 +67,9 @@ ENTRY(_main)
* Set up initial C runtime environment and call board_init_f(0).
*/
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
ldr r0, =(CONFIG_TPL_STACK)
#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
#else
ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)

4
arch/arm/lib/vectors.S
View File

@ -67,11 +67,7 @@
* (1) defines '_start:' as appropriate
* (2) inserts the vector table using ARM_VECTORS as appropriate
*/
#ifdef CONFIG_ARCH_ROCKCHIP
#include <asm/arch-rockchip/boot0.h>
#else
#include <asm/arch/boot0.h>
#endif
#else
/*

76
arch/arm/mach-rockchip/Kconfig
View File

@ -47,14 +47,40 @@ config ROCKCHIP_RK322X
bool "Support Rockchip RK3228/RK3229"
select CPU_V7A
select SUPPORT_SPL
select SUPPORT_TPL
select SPL
select SPL_DM
select SPL_OF_LIBFDT
select TPL
select TPL_DM
select TPL_OF_LIBFDT
select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
select TPL_NEEDS_SEPARATE_STACK if TPL
select SPL_DRIVERS_MISC_SUPPORT
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
select ROCKCHIP_BROM_HELPER
select TPL_LIBCOMMON_SUPPORT
select TPL_LIBGENERIC_SUPPORT
help
The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
including NEON and GPU, Mali-400 graphics, several DDR3 options
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
if ROCKCHIP_RK322X
config TPL_TEXT_BASE
default 0x10081000
config TPL_MAX_SIZE
default 28672
config TPL_STACK
default 0x10088000
endif
config ROCKCHIP_RK3288
bool "Support Rockchip RK3288"
select CPU_V7A
@ -128,12 +154,44 @@ config ROCKCHIP_RK3399
bool "Support Rockchip RK3399"
select ARM64
select SUPPORT_SPL
select SUPPORT_TPL
select SPL
select SPL_ATF
select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
select SPL_LOAD_FIT
select SPL_CLK if SPL
select SPL_PINCTRL if SPL
select SPL_RAM if SPL
select SPL_REGMAP if SPL
select SPL_SYSCON if SPL
select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
select TPL_NEEDS_SEPARATE_STACK if TPL
select SPL_SEPARATE_BSS
select SPL_SERIAL_SUPPORT
select SPL_DRIVERS_MISC_SUPPORT
select CLK
select FIT
select PINCTRL
select RAM
select REGMAP
select SYSCON
select DM_PMIC
select DM_REGULATOR_FIXED
select BOARD_LATE_INIT
select ROCKCHIP_BROM_HELPER
imply TPL_SERIAL_SUPPORT
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_SYS_MALLOC_SIMPLE
imply TPL_BOOTROM_SUPPORT
imply TPL_DRIVERS_MISC_SUPPORT
imply TPL_OF_CONTROL
imply TPL_DM
imply TPL_REGMAP
imply TPL_SYSCON
imply TPL_RAM
imply TPL_CLK
imply TPL_TINY_MEMSET
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
and quad-core Cortex-A53.
@ -142,6 +200,22 @@ config ROCKCHIP_RK3399
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
if ROCKCHIP_RK3399
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
config TPL_TEXT_BASE
default 0xff8c2000
config TPL_MAX_SIZE
default 188416
config TPL_STACK
default 0xff8effff
endif
config ROCKCHIP_RV1108
bool "Support Rockchip RV1108"
select CPU_V7A
@ -169,7 +243,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM
config TPL_ROCKCHIP_BACK_TO_BROM
bool "TPL returns to bootrom"
default y if ROCKCHIP_RK3368
default y
select ROCKCHIP_BROM_HELPER
depends on TPL
help

4
arch/arm/mach-rockchip/Makefile
View File

@ -11,10 +11,12 @@ obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o
obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o
obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o
obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o

46
arch/arm/mach-rockchip/rk322x-board-spl.c
View File

@ -4,55 +4,43 @@
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/timer.h>
u32 spl_boot_device(void)
{
return BOOT_DEVICE_MMC1;
}
u32 spl_boot_mode(const u32 boot_device)
{
return MMCSD_MODE_RAW;
}
#define SGRF_DDR_CON0 0x10150000
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
#ifdef CONFIG_DEBUG_UART
/*
* Debug UART can be used from here if required:
*
* debug_uart_init();
* printch('a');
* printhex8(0x1234);
* printascii("string");
*/
debug_uart_init();
printascii("SPL Init");
#endif
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
printf("spl_early_init() failed: %d\n", ret);
hang();
}
rockchip_timer_init();
printf("timer init done\n");
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
printf("DRAM init failed: %d\n", ret);
return;
}
preloader_console_init();
/* Disable the ddr secure region setting to make it non-secure */
rk_clrreg(SGRF_DDR_CON0, 0x4000);
#if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif

53
arch/arm/mach-rockchip/rk322x-board-tpl.c Normal file
View File

@ -0,0 +1,53 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/timer.h>
u32 spl_boot_device(void)
{
return BOOT_DEVICE_MMC1;
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
/*
* Debug UART can be used from here if required:
*
* debug_uart_init();
* printch('a');
* printhex8(0x1234);
* printascii("string");
*/
debug_uart_init();
printascii("TPL Init");
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
rockchip_timer_init();
printf("timer init done\n");
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
printf("DRAM init failed: %d\n", ret);
return;
}
#if defined(CONFIG_TPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_TPL_BOARD_INIT)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
}

15
arch/arm/mach-rockchip/rk3368-board-spl.c
View File

@ -10,11 +10,9 @@
#include <spl.h>
#include <asm/io.h>
#include <asm/arch-rockchip/periph.h>
#include <dm/pinctrl.h>
void board_init_f(ulong dummy)
{
struct udevice *pinctrl;
struct udevice *dev;
int ret;
@ -24,19 +22,6 @@ void board_init_f(ulong dummy)
hang();
}
/* Set up our preloader console */
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
pr_err("%s: pinctrl init failed: %d\n", __func__, ret);
hang();
}
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0);
if (ret) {
pr_err("%s: failed to set up console UART\n", __func__);
hang();
}
preloader_console_init();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);

40
arch/arm/mach-rockchip/rk3368/rk3368.c
View File

@ -124,6 +124,46 @@ void board_debug_uart_init(void)
GPIO2D0_MASK, GPIO2D0_UART0_SIN);
rk_clrsetreg(&grf->gpio2d_iomux,
GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
struct rk3368_pmu_grf * const pmugrf __maybe_unused =
(struct rk3368_pmu_grf * const)0xff738000;
enum {
/* UART4 */
GPIO0D2_MASK = GENMASK(5, 4),
GPIO0D2_GPIO = 0,
GPIO0D2_UART4_SOUT = (3 << 4),
GPIO0D3_MASK = GENMASK(7, 6),
GPIO0D3_GPIO = 0,
GPIO0D3_UART4_SIN = (3 << 6),
};
/* Enable early UART4 on the PX5 */
rk_clrsetreg(&pmugrf->gpio0d_iomux,
GPIO0D2_MASK | GPIO0D3_MASK,
GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
struct rk3368_grf * const grf =
(struct rk3368_grf * const)0xff770000;
enum {
GPIO2A6_SHIFT = 12,
GPIO2A6_MASK = GENMASK(13, 12),
GPIO2A6_GPIO = 0,
GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
GPIO2A5_SHIFT = 10,
GPIO2A5_MASK = GENMASK(11, 10),
GPIO2A5_GPIO = 0,
GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
};
/* Enable early UART2 on the RK3368 */
rk_clrsetreg(&grf->gpio2a_iomux,
GPIO2A6_MASK, GPIO2A6_UART2_SIN);
rk_clrsetreg(&grf->gpio2a_iomux,
GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
#endif
}
#endif

84
arch/arm/mach-rockchip/rk3399-board-tpl.c Normal file
View File

@ -0,0 +1,84 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#define TIMER_CHN10_BASE 0xff8680a0
#define TIMER_END_COUNT_L 0x00
#define TIMER_END_COUNT_H 0x04
#define TIMER_INIT_COUNT_L 0x10
#define TIMER_INIT_COUNT_H 0x14
#define TIMER_CONTROL_REG 0x1c
#define TIMER_EN 0x1
#define TIMER_FMODE (0 << 1)
#define TIMER_RMODE (1 << 1)
void secure_timer_init(void)
{
writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
/*
* Debug UART can be used from here if required:
*
* debug_uart_init();
* printch('a');
* printhex8(0x1234);
* printascii("string");
*/
printascii("U-Boot TPL board init\n");
#endif
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
secure_timer_init();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
pr_err("DRAM init failed: %d\n", ret);
return;
}
}
void board_return_to_bootrom(void)
{
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_BOOTROM;
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif

94
arch/arm/mach-rockchip/u-boot-tpl-v8.lds Normal file
View File

@ -0,0 +1,94 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019
* Rockchip Electronics Co., Ltd
* Kever Yang<kever.yang@rock-chips.com>
*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Aneesh V <aneesh@ti.com>
*/
OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
.text : {
. = ALIGN(8);
*(.__image_copy_start)
CPUDIR/start.o (.text*)
*(.text*)
}
.rodata : {
. = ALIGN(8);
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.data : {
. = ALIGN(8);
*(.data*)
}
.u_boot_list : {
. = ALIGN(8);
KEEP(*(SORT(.u_boot_list*)));
}
.image_copy_end : {
. = ALIGN(8);
*(.__image_copy_end)
}
.end : {
. = ALIGN(8);
*(.__end)
}
_image_binary_end = .;
.bss_start (NOLOAD) : {
. = ALIGN(8);
KEEP(*(.__bss_start));
}
.bss (NOLOAD) : {
*(.bss*)
. = ALIGN(8);
}
.bss_end (NOLOAD) : {
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}
#if defined(CONFIG_TPL_MAX_SIZE)
ASSERT(__image_copy_end - __image_copy_start < (CONFIG_TPL_MAX_SIZE), \
"TPL image too big");
#endif
#if defined(CONFIG_TPL_BSS_MAX_SIZE)
ASSERT(__bss_end - __bss_start < (CONFIG_TPL_BSS_MAX_SIZE), \
"TPL image BSS too big");
#endif
#if defined(CONFIG_TPL_MAX_FOOTPRINT)
ASSERT(__bss_end - _start < (CONFIG_TPL_MAX_FOOTPRINT), \
"TPL image plus BSS too big");
#endif

12
arch/arm/mach-rockchip/u-boot-tpl.lds Normal file
View File

@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Rockchip Electronic Co.,Ltd
*/
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE
#undef CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE
#include "../cpu/u-boot-spl.lds"

72
board/rockchip/evb_rk3229/README Normal file
View File

@ -0,0 +1,72 @@
Get the Source and prebuild binary
==================================
> mkdir ~/evb_rk3229
> cd ~/evb_rk3229
> git clone git://git.denx.de/u-boot.git
> git clone https://github.com/OP-TEE/optee_os.git
> git clone https://github.com/rockchip-linux/rkbin.git
> git clone https://github.com/rockchip-linux/rkdeveloptool.git
Compile the OP-TEE
===============
> cd optee_os
> make clean
> make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x
Get tee.bin in this step, copy it to U-Boot root dir:
> cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin
Compile the U-Boot
==================
> cd ../u-boot
> export CROSS_COMPILE=arm-linux-gnueabihf-
> export ARCH=arm
> make evb-rk3229_defconfig
> make
> make u-boot.itb
Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step.
Compile the rkdeveloptool
=======================
Follow instructions in latest README
> cd ../rkflashtool
> autoreconf -i
> ./configure
> make
> sudo make install
Get rkdeveloptool in you Host in this step.
Both origin binaries and Tool are ready now, choose either option 1 or
option 2 to deploy U-Boot.
Package the image
=================
> cd ../u-boot
> tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img
> cat spl/u-boot-spl.bin >> idbloader.img
Get idbloader.img in this step.
Flash the image to eMMC
=======================
Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
> cd ..
> rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin
> rkdeveloptool wl 64 u-boot/idbloader.img
> rkdeveloptool wl 0x4000 u-boot/u-boot.itb
> rkdeveloptool rd
Flash the image to SD card
==========================
> dd if=u-boot/idbloader.img of=/dev/sdb seek=64
> dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384
You should be able to get U-Boot log message with OP-TEE boot info.
For more detail, please reference to:
http://opensource.rock-chips.com/wiki_Boot_option

12
board/rockchip/evb_rk3399/MAINTAINERS
View File

@ -6,6 +6,18 @@ F: include/configs/evb_rk3399.h
F: configs/evb-rk3399_defconfig
F: configs/firefly-rk3399_defconfig
NANOPC-T4
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/nanopc-t4-rk3399_defconfig
F: arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
NANOPI-M4
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/nanopi-m4-rk3399_defconfig
F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
ORANGEPI-RK3399
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained

1
configs/am65x_evm_a53_defconfig
View File

@ -72,4 +72,5 @@ CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_TI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y

1
configs/am65x_evm_r5_defconfig
View File

@ -83,6 +83,7 @@ CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y

1
configs/am65x_hs_evm_a53_defconfig
View File

@ -75,4 +75,5 @@ CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_TI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y

1
configs/am65x_hs_evm_r5_defconfig
View File

@ -85,6 +85,7 @@ CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y

17
configs/chromebook_bob_defconfig
View File

@ -17,9 +17,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
@ -27,8 +24,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
@ -47,12 +42,6 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
@ -72,16 +61,10 @@ CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y

5
configs/chromebook_minnie_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SOUND=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
@ -74,6 +75,10 @@ CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_I2S_ROCKCHIP=y
CONFIG_SOUND_MAX98090=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y

1
configs/chromebook_samus_tpl_defconfig
View File

@ -73,6 +73,7 @@ CONFIG_SOUND=y
CONFIG_SOUND_I8254=y
CONFIG_SOUND_RT5677=y
CONFIG_SPI=y
CONFIG_TPL_SYSRESET=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y

56
configs/evb-px5_defconfig
View File

@ -1,30 +1,82 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3368=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_EVB_PX5=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xFF1c0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_BOOTSTAGE=y
CONFIG_SPL_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
CONFIG_TPL_BOOTROM_SUPPORT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_TPL_CLK=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_TPL_TIMER=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_PANIC_HANG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

27
configs/evb-rk3229_defconfig
View File

@ -1,38 +1,52 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_SYS_TEXT_BASE=0x61000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ROCKCHIP_RK322X=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TARGET_EVB_RK3229=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_SPL_STACK_R_ADDR=0x60600000
CONFIG_DEBUG_UART_BASE=0x11030000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="arch/arm/mach-rockchip/fit_spl_optee.its"
CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0x10081000
CONFIG_SPL_TEXT_BASE=0x60000000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_SPL_OPTEE=y
CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_TPL_CLK=y
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
@ -47,6 +61,7 @@ CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
@ -57,4 +72,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

24
configs/evb-rk3399_defconfig
View File

@ -5,23 +5,18 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
@ -34,12 +29,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
@ -49,16 +38,10 @@ CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
@ -79,4 +62,5 @@ CONFIG_VIDEO_ROCKCHIP=y
CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
CONFIG_DISPLAY_ROCKCHIP_MIPI=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

17
configs/ficus-rk3399_defconfig
View File

@ -11,16 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
@ -33,12 +28,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
@ -50,17 +39,11 @@ CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y

24
configs/firefly-rk3399_defconfig
View File

@ -5,23 +5,18 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
@ -33,12 +28,6 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
@ -49,16 +38,10 @@ CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
@ -74,4 +57,5 @@ CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

1
configs/mt7629_rfb_defconfig
View File

@ -65,6 +65,7 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTK_QSPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y

59
configs/nanopc-t4-rk3399_defconfig Normal file
View File

@ -0,0 +1,59 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopc-t4"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_ERRNO_STR=y

59
configs/nanopi-m4-rk3399_defconfig Normal file
View File

@ -0,0 +1,59 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_ERRNO_STR=y

18
configs/orangepi-rk3399_defconfig
View File

@ -11,16 +11,12 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
@ -32,12 +28,6 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
@ -47,16 +37,10 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y

16
configs/puma-rk3399_defconfig
View File

@ -15,8 +15,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_MISC_INIT_R=y
@ -32,8 +30,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@ -52,12 +48,6 @@ CONFIG_OF_LIVE=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-ddr1600"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
@ -76,20 +66,14 @@ CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_DM_RTC=y
CONFIG_RTC_ISL1208=y
CONFIG_DEBUG_UART_SHIFT=2

17
configs/rock960-rk3399_defconfig
View File

@ -11,17 +11,12 @@ CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_SYS_PROMPT="rock960 => "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
@ -34,12 +29,6 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
@ -47,16 +36,10 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y

1
configs/sandbox_spl_defconfig
View File

@ -174,6 +174,7 @@ CONFIG_SANDBOX_SPI=y
CONFIG_SPMI=y
CONFIG_SPMI_SANDBOX=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_TIMER=y
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y

233
doc/README.rockchip
View File

@ -88,10 +88,92 @@ One RV3188 baord is supported:
For example:
1. To build RK3288 board:
CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all
(or you can use another cross compiler if you prefer)
(or you can use another cross compiler if you prefer)
2. To build RK3399 board:
Option 1: Package the image with Rockchip miniloader:
- Compile U-Boot
=> cd /path/to/u-boot
=> make nanopi-neo4-rk3399_defconfig
=> make
=> make u-boot.itb
- Get the rkbin
=> git clone https://github.com/rockchip-linux/rkbin.git
- Create trust.img
=> cd /path/to/rkbin
=> ./tools/trust_merger RKTRUST/RK3399TRUST.ini
- Create uboot.img
=> cd /path/to/rkbin
=> ./tools/loaderimage --pack --uboot /path/to/u-boot/u-boot-dtb.bin uboot.img
(Get trust.img and uboot.img)
Option 2: Package the image with SPL:
- We need the Python elftools.elf.elffile library for make_fit_atf.py to work
=> sudo apt-get install python-pyelftools
- Export cross compiler path for aarch64
- Compile ATF
For Puma board.
=> git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
=> cd arm-trusted-firmware
=> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
(copy bl31.bin into U-Boot root dir)
=> cp build/rk3399/release/bl31/bl31.bin /path/to/u-boot/bl31-rk3399.bin
For rest of rk3399 boards.
=> git clone https://github.com/ARM-software/arm-trusted-firmware.git
=> cd arm-trusted-firmware
(export cross compiler path for Cortex-M0 MCU likely arm-none-eabi-)
=> make realclean
=> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
(copy bl31.elf into U-Boot root dir)
=> cp build/rk3399/release/bl31/bl31.elf /path/to/u-boot
- Compile PMU M0 firmware
This is optional for most of the rk3399 boards and required only for Puma board.
=> git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git
=> cd rk3399-cortex-m0
(export cross compiler path for Cortex-M0 PMU)
=> make CROSS_COMPILE=arm-cortex_m0-eabi-
(copy rk3399m0.bin into U-Boot root dir)
=> cp rk3399m0.bin /path/to/u-boot
- Compile U-Boot
=> cd /path/to/u-boot
=> make orangepi-rk3399_defconfig
=> make
=> make u-boot.itb
(Get spl/u-boot-spl-dtb.bin, u-boot.itb images and some boards would get
spl/u-boot-spl.bin since it doesn't enable CONFIG_SPL_OF_CONTROL)
Writing to the board with USB
=============================
@ -225,6 +307,153 @@ tools/mkimage -n rk3188 -T rksd -d spl/u-boot-spl.bin out
truncate -s %2048 u-boot.bin
cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 7C4E0304550509072D2C7B38170D1711' >> out
Booting from an SD card on RK3399
=================================
To write an image that boots from an SD card (assumed to be /dev/sdc):
Option 1: Package the image with Rockchip miniloader:
- Create idbloader.img
=> cd /path/to/u-boot
=> ./tools/mkimage -n rk3399 -T rksd -d /path/to/rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin idbloader.img
=> cat /path/to/rkbin/bin/rk33/rk3399_miniloader_v1.19.bin >> idbloader.img
- Write idbloader.img at 64 sector
=> sudo dd if=idbloader.img of=/dev/sdc seek=64
- Write trust.img at 24576
=> sudo dd if=trust.img of=/dev/sdc seek=24576
- Write uboot.img at 16384 sector
=> sudo dd if=uboot.img of=/dev/sdc seek=16384
=> sync
Put this SD (or micro-SD) card into your board and reset it. You should see
something like:
DDR Version 1.20 20190314
In
Channel 0: DDR3, 933MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
no stride
ch 0 ddrconfig = 0x101, ddrsize = 0x20
pmugrf_os_reg[2] = 0x10006281, stride = 0x17
OUT
Boot1: 2019-03-14, version: 1.19
CPUId = 0x0
ChipType = 0x10, 239
mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000
mmc: ERROR: Card did not respond to voltage select!
emmc reinit
mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000
mmc: ERROR: Card did not respond to voltage select!
emmc reinit
mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000
mmc: ERROR: Card did not respond to voltage select!
SdmmcInit=2 1
mmc0:cmd5,20
SdmmcInit=0 0
BootCapSize=0
UserCapSize=60543MB
FwPartOffset=2000 , 0
StorageInit ok = 45266
SecureMode = 0
SecureInit read PBA: 0x4
SecureInit read PBA: 0x404
SecureInit read PBA: 0x804
SecureInit read PBA: 0xc04
SecureInit read PBA: 0x1004
SecureInit read PBA: 0x1404
SecureInit read PBA: 0x1804
SecureInit read PBA: 0x1c04
SecureInit ret = 0, SecureMode = 0
atags_set_bootdev: ret:(0)
GPT 0x3380ec0 signature is wrong
recovery gpt...
GPT 0x3380ec0 signature is wrong
recovery gpt fail!
LoadTrust Addr:0x4000
No find bl30.bin
Load uboot, ReadLba = 2000
hdr 0000000003380880 + 0x0:0x88,0x41,0x3e,0x97,0xe6,0x61,0x54,0x23,0xe9,0x5a,0xd1,0x2b,0xdc,0x2f,0xf9,0x35,
Load OK, addr=0x200000, size=0x9c9c0
RunBL31 0x10000
NOTICE: BL31: v1.3(debug):370ab80
NOTICE: BL31: Built : 09:23:41, Mar 4 2019
NOTICE: BL31: Rockchip release version: v1.1
INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
INFO: Using opteed sec cpu_context!
INFO: boot cpu mask: 0
INFO: plat_rockchip_pmu_init(1181): pd status 3e
INFO: BL31: Initializing runtime services
INFO: BL31: Initializing BL32
INF [0x0] TEE-CORE:init_primary_helper:337: Initializing (1.1.0-195-g8f090d20 #6 Fri Dec 7 06:11:20 UTC 2018 aarch64)
INF [0x0] TEE-CORE:init_primary_helper:338: Release version: 1.2
INF [0x0] TEE-CORE:init_teecore:83: teecore inits done
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x200000
INFO: SPSR = 0x3c9
U-Boot 2019.04-rc4-00136-gfd121f9641-dirty (Apr 16 2019 - 14:02:47 +0530)
Model: FriendlyARM NanoPi NEO4
DRAM: 1022 MiB
MMC: dwmmc@fe310000: 2, dwmmc@fe320000: 1, sdhci@fe330000: 0
Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@ff1a0000
Out: serial@ff1a0000
Err: serial@ff1a0000
Model: FriendlyARM NanoPi NEO4
Net: eth0: ethernet@fe300000
Hit any key to stop autoboot: 0
=>
Option 2: Package the image with SPL:
- Prefix rk3399 header to SPL image
=> cd /path/to/u-boot
=> ./tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl-dtb.bin out
- Write prefixed SPL at 64th sector
=> sudo dd if=out of=/dev/sdc seek=64
- Write U-Boot proper at 16384 sector
=> sudo dd if=u-boot.itb of=/dev/sdc seek=16384
=> sync
Put this SD (or micro-SD) card into your board and reset it. You should see
something like:
U-Boot SPL board init
Trying to boot from MMC1
U-Boot 2019.01-00004-g14db5ee998 (Mar 11 2019 - 13:18:41 +0530)
Model: Orange Pi RK3399 Board
DRAM: 2 GiB
MMC: dwmmc@fe310000: 2, dwmmc@fe320000: 1, sdhci@fe330000: 0
Loading Environment from MMC... OK
In: serial@ff1a0000
Out: serial@ff1a0000
Err: serial@ff1a0000
Model: Orange Pi RK3399 Board
Net: eth0: ethernet@fe300000
Hit any key to stop autoboot: 0
=>
Using fastboot on rk3288
========================
@ -385,5 +614,7 @@ There are some documents about partitions in the links below.
http://rockchip.wikidot.com/partitions
--
Jagan Teki <jagan@amarulasolutions.com>
27 Mar 2019
Simon Glass <sjg@chromium.org>
24 June 2015

6
drivers/clk/rockchip/clk_rk322x.c
View File

@ -121,10 +121,10 @@ static void rkclk_init(struct rk322x_cru *cru)
assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
rk_clrsetreg(&cru->cru_clksel_con[0],
BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
@ -217,6 +217,7 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
case SCLK_EMMC_SAMPLE:
con = readl(&cru->cru_clksel_con[11]);
mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
con = readl(&cru->cru_clksel_con[12]);
@ -293,6 +294,7 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
case SCLK_EMMC_SAMPLE:
rk_clrsetreg(&cru->cru_clksel_con[11],
EMMC_PLL_MASK,
mux << EMMC_PLL_SHIFT);

56
drivers/pinctrl/rockchip/pinctrl-rk3036.c
View File

@ -11,6 +11,30 @@
#include "pinctrl-rockchip.h"
static int rk3036_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
u32 data;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
data = (mask << (bit + 16));
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3036_PULL_OFFSET 0x118
#define RK3036_PULL_PINS_PER_REG 16
#define RK3036_PULL_BANK_STRIDE 8
@ -29,6 +53,27 @@ static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = pin_num % RK3036_PULL_PINS_PER_REG;
};
static int rk3036_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct regmap *regmap;
int reg, ret;
u8 bit;
u32 data;
if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
pull != PIN_CONFIG_BIAS_DISABLE)
return -ENOTSUPP;
rk3036_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
data = BIT(bit + 16);
if (pull == PIN_CONFIG_BIAS_DISABLE)
data |= BIT(bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
static struct rockchip_pin_bank rk3036_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
@ -36,12 +81,11 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = {
};
static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
.pin_banks = rk3036_pin_banks,
.nr_banks = ARRAY_SIZE(rk3036_pin_banks),
.label = "RK3036-GPIO",
.type = RK3036,
.grf_mux_offset = 0xa8,
.pull_calc_reg = rk3036_calc_pull_reg_and_bit,
.pin_banks = rk3036_pin_banks,
.nr_banks = ARRAY_SIZE(rk3036_pin_banks),
.grf_mux_offset = 0xa8,
.set_mux = rk3036_set_mux,
.set_pull = rk3036_set_pull,
};
static const struct udevice_id rk3036_pinctrl_ids[] = {

62
drivers/pinctrl/rockchip/pinctrl-rk3128.c
View File

@ -98,6 +98,42 @@ static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
},
};
static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
u32 data, route_reg, route_val;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
if (bank->route_mask & BIT(pin)) {
if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
&route_val)) {
ret = regmap_write(regmap, route_reg, route_val);
if (ret)
return ret;
}
}
data = (mask << (bit + 16));
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3128_PULL_OFFSET 0x118
#define RK3128_PULL_PINS_PER_REG 16
#define RK3128_PULL_BANK_STRIDE 8
@ -116,6 +152,27 @@ static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = pin_num % RK3128_PULL_PINS_PER_REG;
}
static int rk3128_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct regmap *regmap;
int reg, ret;
u8 bit;
u32 data;
if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
pull != PIN_CONFIG_BIAS_DISABLE)
return -ENOTSUPP;
rk3128_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
data = BIT(bit + 16);
if (pull == PIN_CONFIG_BIAS_DISABLE)
data |= BIT(bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
static struct rockchip_pin_bank rk3128_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
@ -126,14 +183,13 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = {
static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
.pin_banks = rk3128_pin_banks,
.nr_banks = ARRAY_SIZE(rk3128_pin_banks),
.label = "RK3128-GPIO",
.type = RK3128,
.grf_mux_offset = 0xa8,
.iomux_recalced = rk3128_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
.iomux_routes = rk3128_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
.pull_calc_reg = rk3128_calc_pull_reg_and_bit,
.set_mux = rk3128_set_mux,
.set_pull = rk3128_set_pull,
};
static const struct udevice_id rk3128_pinctrl_ids[] = {

62
drivers/pinctrl/rockchip/pinctrl-rk3188.c
View File

@ -11,6 +11,30 @@
#include "pinctrl-rockchip.h"
static int rk3188_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
u32 data;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
data = (mask << (bit + 16));
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3188_PULL_OFFSET 0x164
#define RK3188_PULL_PMU_OFFSET 0x64
@ -47,6 +71,33 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
}
}
static int rk3188_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct regmap *regmap;
int reg, ret;
u8 bit, type;
u32 data;
if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
return -ENOTSUPP;
rk3188_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
type = bank->pull_type[pin_num / 8];
ret = rockchip_translate_pull_value(type, pull);
if (ret < 0) {
debug("unsupported pull setting %d\n", pull);
return ret;
}
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
static struct rockchip_pin_bank rk3188_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
PIN_BANK(1, 32, "gpio1"),
@ -55,12 +106,11 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = {
};
static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
.pin_banks = rk3188_pin_banks,
.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
.label = "RK3188-GPIO",
.type = RK3188,
.grf_mux_offset = 0x60,
.pull_calc_reg = rk3188_calc_pull_reg_and_bit,
.pin_banks = rk3188_pin_banks,
.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
.grf_mux_offset = 0x60,
.set_mux = rk3188_set_mux,
.set_pull = rk3188_set_pull,
};
static const struct udevice_id rk3188_pinctrl_ids[] = {

100
drivers/pinctrl/rockchip/pinctrl-rk322x.c
View File

@ -141,6 +141,39 @@ static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
},
};
static int rk3228_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
u32 data, route_reg, route_val;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
if (bank->route_mask & BIT(pin)) {
if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
&route_val)) {
ret = regmap_write(regmap, route_reg, route_val);
if (ret)
return ret;
}
}
data = (mask << (bit + 16));
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3228_PULL_OFFSET 0x100
static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
@ -158,6 +191,33 @@ static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
}
static int rk3228_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct regmap *regmap;
int reg, ret;
u8 bit, type;
u32 data;
if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
return -ENOTSUPP;
rk3228_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
type = bank->pull_type[pin_num / 8];
ret = rockchip_translate_pull_value(type, pull);
if (ret < 0) {
debug("unsupported pull setting %d\n", pull);
return ret;
}
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3228_DRV_GRF_OFFSET 0x200
static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
@ -175,6 +235,29 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
}
static int rk3228_set_drive(struct rockchip_pin_bank *bank,
int pin_num, int strength)
{
struct regmap *regmap;
int reg, ret;
u32 data;
u8 bit;
int type = bank->drv[pin_num / 8].drv_type;
rk3228_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
ret = rockchip_translate_drive_value(type, strength);
if (ret < 0) {
debug("unsupported driver strength %d\n", strength);
return ret;
}
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
static struct rockchip_pin_bank rk3228_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
@ -183,15 +266,14 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = {
};
static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
.pin_banks = rk3228_pin_banks,
.nr_banks = ARRAY_SIZE(rk3228_pin_banks),
.label = "RK3228-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
.iomux_routes = rk3228_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
.pull_calc_reg = rk3228_calc_pull_reg_and_bit,
.drv_calc_reg = rk3228_calc_drv_reg_and_bit,
.pin_banks = rk3228_pin_banks,
.nr_banks = ARRAY_SIZE(rk3228_pin_banks),
.grf_mux_offset = 0x0,
.iomux_routes = rk3228_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
.set_mux = rk3228_set_mux,
.set_pull = rk3228_set_pull,
.set_drive = rk3228_set_drive,
};
static const struct udevice_id rk3228_pinctrl_ids[] = {

167
drivers/pinctrl/rockchip/pinctrl-rk3288.c
View File

@ -7,7 +7,6 @@
#include <dm.h>
#include <dm/pinctrl.h>
#include <regmap.h>
#include <syscon.h>
#include "pinctrl-rockchip.h"
@ -29,6 +28,47 @@ static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
},
};
static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
u32 data, route_reg, route_val;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
if (bank->route_mask & BIT(pin)) {
if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
&route_val)) {
ret = regmap_write(regmap, route_reg, route_val);
if (ret)
return ret;
}
}
/* bank0 is special, there are no higher 16 bit writing bits. */
if (bank->bank_num == 0) {
regmap_read(regmap, reg, &data);
data &= ~(mask << bit);
} else {
/* enable the write to the equivalent lower bits */
data = (mask << (bit + 16));
}
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3288_PULL_OFFSET 0x140
#define RK3288_PULL_PMU_OFFSET 0x64
@ -42,10 +82,6 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
if (bank->bank_num == 0) {
*regmap = priv->regmap_pmu;
*reg = RK3288_PULL_PMU_OFFSET;
*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
*bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
} else {
*regmap = priv->regmap_base;
*reg = RK3288_PULL_OFFSET;
@ -53,11 +89,46 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
}
*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
}
static int rk3288_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct regmap *regmap;
int reg, ret;
u8 bit, type;
u32 data;
if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
return -ENOTSUPP;
rk3288_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
type = bank->pull_type[pin_num / 8];
ret = rockchip_translate_pull_value(type, pull);
if (ret < 0) {
debug("unsupported pull setting %d\n", pull);
return ret;
}
/* bank0 is special, there are no higher 16 bit writing bits */
if (bank->bank_num == 0) {
regmap_read(regmap, reg, &data);
data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit);
} else {
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
}
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3288_DRV_PMU_OFFSET 0x70
@ -73,10 +144,6 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
if (bank->bank_num == 0) {
*regmap = priv->regmap_pmu;
*reg = RK3288_DRV_PMU_OFFSET;
*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
*bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
} else {
*regmap = priv->regmap_base;
*reg = RK3288_DRV_GRF_OFFSET;
@ -84,27 +151,48 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
}
*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
}
static int rk3288_set_drive(struct rockchip_pin_bank *bank,
int pin_num, int strength)
{
struct regmap *regmap;
int reg, ret;
u32 data;
u8 bit;
int type = bank->drv[pin_num / 8].drv_type;
rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
ret = rockchip_translate_drive_value(type, strength);
if (ret < 0) {
debug("unsupported driver strength %d\n", strength);
return ret;
}
/* bank0 is special, there are no higher 16 bit writing bits. */
if (bank->bank_num == 0) {
regmap_read(regmap, reg, &data);
data &= ~(((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << bit);
} else {
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
}
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
static struct rockchip_pin_bank rk3288_pin_banks[] = {
PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0",
IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
IOMUX_UNROUTED,
DRV_TYPE_WRITABLE_32BIT,
DRV_TYPE_WRITABLE_32BIT,
DRV_TYPE_WRITABLE_32BIT,
0,
PULL_TYPE_WRITABLE_32BIT,
PULL_TYPE_WRITABLE_32BIT,
PULL_TYPE_WRITABLE_32BIT,
0
PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_UNROUTED
),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
IOMUX_UNROUTED,
@ -133,16 +221,15 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = {
};
static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
.pin_banks = rk3288_pin_banks,
.nr_banks = ARRAY_SIZE(rk3288_pin_banks),
.label = "RK3288-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
.pmu_mux_offset = 0x84,
.iomux_routes = rk3288_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
.pull_calc_reg = rk3288_calc_pull_reg_and_bit,
.drv_calc_reg = rk3288_calc_drv_reg_and_bit,
.pin_banks = rk3288_pin_banks,
.nr_banks = ARRAY_SIZE(rk3288_pin_banks),
.grf_mux_offset = 0x0,
.pmu_mux_offset = 0x84,
.iomux_routes = rk3288_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
.set_mux = rk3288_set_mux,
.set_pull = rk3288_set_pull,
.set_drive = rk3288_set_drive,
};
static const struct udevice_id rk3288_pinctrl_ids[] = {

125
drivers/pinctrl/rockchip/pinctrl-rk3328.c
View File

@ -121,6 +121,42 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
},
};
static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
u32 data, route_reg, route_val;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
if (bank->route_mask & BIT(pin)) {
if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
&route_val)) {
ret = regmap_write(regmap, route_reg, route_val);
if (ret)
return ret;
}
}
data = (mask << (bit + 16));
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3328_PULL_OFFSET 0x100
static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
@ -138,6 +174,33 @@ static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
}
static int rk3328_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct regmap *regmap;
int reg, ret;
u8 bit, type;
u32 data;
if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
return -ENOTSUPP;
rk3328_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
type = bank->pull_type[pin_num / 8];
ret = rockchip_translate_pull_value(type, pull);
if (ret < 0) {
debug("unsupported pull setting %d\n", pull);
return ret;
}
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3328_DRV_GRF_OFFSET 0x200
static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
@ -155,6 +218,30 @@ static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
}
static int rk3328_set_drive(struct rockchip_pin_bank *bank,
int pin_num, int strength)
{
struct regmap *regmap;
int reg, ret;
u32 data;
u8 bit;
int type = bank->drv[pin_num / 8].drv_type;
rk3328_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
ret = rockchip_translate_drive_value(type, strength);
if (ret < 0) {
debug("unsupported driver strength %d\n", strength);
return ret;
}
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3328_SCHMITT_BITS_PER_PIN 1
#define RK3328_SCHMITT_PINS_PER_REG 16
#define RK3328_SCHMITT_BANK_STRIDE 8
@ -177,6 +264,21 @@ static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
static int rk3328_set_schmitt(struct rockchip_pin_bank *bank,
int pin_num, int enable)
{
struct regmap *regmap;
int reg;
u8 bit;
u32 data;
rk3328_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
/* enable the write to the equivalent lower bits */
data = BIT(bit + 16) | (enable << bit);
return regmap_write(regmap, reg, data);
}
static struct rockchip_pin_bank rk3328_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
@ -192,18 +294,17 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
};
static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
.pin_banks = rk3328_pin_banks,
.nr_banks = ARRAY_SIZE(rk3328_pin_banks),
.label = "RK3328-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
.iomux_recalced = rk3328_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
.iomux_routes = rk3328_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
.pull_calc_reg = rk3328_calc_pull_reg_and_bit,
.drv_calc_reg = rk3328_calc_drv_reg_and_bit,
.schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
.pin_banks = rk3328_pin_banks,
.nr_banks = ARRAY_SIZE(rk3328_pin_banks),
.grf_mux_offset = 0x0,
.iomux_recalced = rk3328_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
.iomux_routes = rk3328_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
.set_mux = rk3328_set_mux,
.set_pull = rk3328_set_pull,
.set_drive = rk3328_set_drive,
.set_schmitt = rk3328_set_schmitt,
};
static const struct udevice_id rk3328_pinctrl_ids[] = {

115
drivers/pinctrl/rockchip/pinctrl-rk3368.c
View File

@ -11,6 +11,30 @@
#include "pinctrl-rockchip.h"
static int rk3368_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
u32 data;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
data = (mask << (bit + 16));
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3368_PULL_GRF_OFFSET 0x100
#define RK3368_PULL_PMU_OFFSET 0x10
@ -24,10 +48,6 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
if (bank->bank_num == 0) {
*regmap = priv->regmap_pmu;
*reg = RK3368_PULL_PMU_OFFSET;
*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
*bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
} else {
*regmap = priv->regmap_base;
*reg = RK3368_PULL_GRF_OFFSET;
@ -35,11 +55,39 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
}
*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
}
static int rk3368_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct regmap *regmap;
int reg, ret;
u8 bit, type;
u32 data;
if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
return -ENOTSUPP;
rk3368_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
type = bank->pull_type[pin_num / 8];
ret = rockchip_translate_pull_value(type, pull);
if (ret < 0) {
debug("unsupported pull setting %d\n", pull);
return ret;
}
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3368_DRV_PMU_OFFSET 0x20
@ -55,10 +103,6 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
if (bank->bank_num == 0) {
*regmap = priv->regmap_pmu;
*reg = RK3368_DRV_PMU_OFFSET;
*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
*bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
} else {
*regmap = priv->regmap_base;
*reg = RK3368_DRV_GRF_OFFSET;
@ -66,11 +110,35 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
}
*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
}
static int rk3368_set_drive(struct rockchip_pin_bank *bank,
int pin_num, int strength)
{
struct regmap *regmap;
int reg, ret;
u32 data;
u8 bit;
int type = bank->drv[pin_num / 8].drv_type;
rk3368_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
ret = rockchip_translate_drive_value(type, strength);
if (ret < 0) {
debug("unsupported driver strength %d\n", strength);
return ret;
}
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
static struct rockchip_pin_bank rk3368_pin_banks[] = {
@ -85,14 +153,13 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = {
};
static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
.pin_banks = rk3368_pin_banks,
.nr_banks = ARRAY_SIZE(rk3368_pin_banks),
.label = "RK3368-GPIO",
.type = RK3368,
.grf_mux_offset = 0x0,
.pmu_mux_offset = 0x0,
.pull_calc_reg = rk3368_calc_pull_reg_and_bit,
.drv_calc_reg = rk3368_calc_drv_reg_and_bit,
.pin_banks = rk3368_pin_banks,
.nr_banks = ARRAY_SIZE(rk3368_pin_banks),
.grf_mux_offset = 0x0,
.pmu_mux_offset = 0x0,
.set_mux = rk3368_set_mux,
.set_pull = rk3368_set_pull,
.set_drive = rk3368_set_drive,
};
static const struct udevice_id rk3368_pinctrl_ids[] = {

169
drivers/pinctrl/rockchip/pinctrl-rk3399.c
View File

@ -50,6 +50,39 @@ static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
},
};
static int rk3399_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
u32 data, route_reg, route_val;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
if (bank->route_mask & BIT(pin)) {
if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
&route_val)) {
ret = regmap_write(regmap, route_reg, route_val);
if (ret)
return ret;
}
}
data = (mask << (bit + 16));
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3399_PULL_GRF_OFFSET 0xe040
#define RK3399_PULL_PMU_OFFSET 0x40
@ -65,10 +98,6 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*reg = RK3399_PULL_PMU_OFFSET;
*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
*bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
} else {
*regmap = priv->regmap_base;
*reg = RK3399_PULL_GRF_OFFSET;
@ -76,11 +105,39 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
/* correct the offset, as we're starting with the 3rd bank */
*reg -= 0x20;
*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
}
*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
}
static int rk3399_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct regmap *regmap;
int reg, ret;
u8 bit, type;
u32 data;
if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
return -ENOTSUPP;
rk3399_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
type = bank->pull_type[pin_num / 8];
ret = rockchip_translate_pull_value(type, pull);
if (ret < 0) {
debug("unsupported pull setting %d\n", pull);
return ret;
}
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
@ -104,6 +161,79 @@ static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % 8) * 2;
}
static int rk3399_set_drive(struct rockchip_pin_bank *bank,
int pin_num, int strength)
{
struct regmap *regmap;
int reg, ret;
u32 data, rmask_bits, temp;
u8 bit;
int drv_type = bank->drv[pin_num / 8].drv_type;
rk3399_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
ret = rockchip_translate_drive_value(drv_type, strength);
if (ret < 0) {
debug("unsupported driver strength %d\n", strength);
return ret;
}
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
break;
case 15:
/*
* drive-strength offset is special, as it is spread
* over 2 registers, the bit data[15] contains bit 0
* of the value while temp[1:0] contains bits 2 and 1
*/
data = (ret & 0x1) << 15;
temp = (ret >> 0x1) & 0x3;
data |= BIT(31);
ret = regmap_write(regmap, reg, data);
if (ret)
return ret;
temp |= (0x3 << 16);
reg += 0x4;
ret = regmap_write(regmap, reg, temp);
return ret;
case 18 ... 21:
/* setting fully enclosed in the second register */
reg += 4;
bit -= 16;
break;
default:
debug("unsupported bit: %d for pinctrl drive type: %d\n",
bit, drv_type);
return -EINVAL;
}
break;
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
break;
default:
debug("unsupported pinctrl drive type: %d\n",
drv_type);
return -EINVAL;
}
/* enable the write to the equivalent lower bits */
data = ((1 << rmask_bits) - 1) << (bit + 16);
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
static struct rockchip_pin_bank rk3399_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
IOMUX_SOURCE_PMU,
@ -158,18 +288,17 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = {
};
static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
.pin_banks = rk3399_pin_banks,
.nr_banks = ARRAY_SIZE(rk3399_pin_banks),
.label = "RK3399-GPIO",
.type = RK3399,
.grf_mux_offset = 0xe000,
.pmu_mux_offset = 0x0,
.grf_drv_offset = 0xe100,
.pmu_drv_offset = 0x80,
.iomux_routes = rk3399_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
.pull_calc_reg = rk3399_calc_pull_reg_and_bit,
.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
.pin_banks = rk3399_pin_banks,
.nr_banks = ARRAY_SIZE(rk3399_pin_banks),
.grf_mux_offset = 0xe000,
.pmu_mux_offset = 0x0,
.grf_drv_offset = 0xe100,
.pmu_drv_offset = 0x80,
.iomux_routes = rk3399_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
.set_mux = rk3399_set_mux,
.set_pull = rk3399_set_pull,
.set_drive = rk3399_set_drive,
};
static const struct udevice_id rk3399_pinctrl_ids[] = {

282
drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
View File

@ -35,8 +35,8 @@ static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
return 0;
}
static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
int *reg, u8 *bit, int *mask)
void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
int *reg, u8 *bit, int *mask)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
struct rockchip_pin_ctrl *ctrl = priv->ctrl;
@ -58,8 +58,8 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
*bit = data->bit;
}
static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
int mux, u32 *reg, u32 *value)
bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
int mux, u32 *reg, u32 *value)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
struct rockchip_pin_ctrl *ctrl = priv->ctrl;
@ -82,7 +82,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
return true;
}
static int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
{
int offset = 0;
@ -193,11 +193,9 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
struct rockchip_pin_ctrl *ctrl = priv->ctrl;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
u32 data, route_reg, route_val;
int ret;
ret = rockchip_verify_mux(bank, pin, mux);
if (ret < 0)
@ -208,35 +206,10 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
if (!ctrl->set_mux)
return -ENOTSUPP;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
if (bank->route_mask & BIT(pin)) {
if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
&route_val)) {
ret = regmap_write(regmap, route_reg, route_val);
if (ret)
return ret;
}
}
if (mux_type & IOMUX_WRITABLE_32BIT) {
regmap_read(regmap, reg, &data);
data &= ~(mask << bit);
} else {
data = (mask << (bit + 16));
}
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
ret = ctrl->set_mux(bank, pin, mux);
return ret;
}
@ -249,99 +222,37 @@ static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
{ 4, 7, 10, 13, 16, 19, 22, 26 }
};
int rockchip_translate_drive_value(int type, int strength)
{
int i, ret;
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) {
if (rockchip_perpin_drv_list[type][i] == strength) {
ret = i;
break;
} else if (rockchip_perpin_drv_list[type][i] < 0) {
ret = rockchip_perpin_drv_list[type][i];
break;
}
}
return ret;
}
static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
int pin_num, int strength)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
struct rockchip_pin_ctrl *ctrl = priv->ctrl;
struct regmap *regmap;
int reg, ret, i;
u32 data, rmask_bits, temp;
u8 bit;
/* Where need to clean the special mask for rockchip_perpin_drv_list */
int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK);
debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
pin_num, strength);
ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
if (!ctrl->set_drive)
return -ENOTSUPP;
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
if (rockchip_perpin_drv_list[drv_type][i] == strength) {
ret = i;
break;
} else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
ret = rockchip_perpin_drv_list[drv_type][i];
break;
}
}
if (ret < 0) {
debug("unsupported driver strength %d\n", strength);
return ret;
}
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
break;
case 15:
/*
* drive-strength offset is special, as it is spread
* over 2 registers, the bit data[15] contains bit 0
* of the value while temp[1:0] contains bits 2 and 1
*/
data = (ret & 0x1) << 15;
temp = (ret >> 0x1) & 0x3;
data |= BIT(31);
ret = regmap_write(regmap, reg, data);
if (ret)
return ret;
temp |= (0x3 << 16);
reg += 0x4;
ret = regmap_write(regmap, reg, temp);
return ret;
case 18 ... 21:
/* setting fully enclosed in the second register */
reg += 4;
bit -= 16;
break;
default:
debug("unsupported bit: %d for pinctrl drive type: %d\n",
bit, drv_type);
return -EINVAL;
}
break;
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
break;
default:
debug("unsupported pinctrl drive type: %d\n",
drv_type);
return -EINVAL;
}
if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) {
regmap_read(regmap, reg, &data);
data &= ~(((1 << rmask_bits) - 1) << bit);
} else {
/* enable the write to the equivalent lower bits */
data = ((1 << rmask_bits) - 1) << (bit + 16);
}
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
return ctrl->set_drive(bank, pin_num, strength);
}
static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
@ -359,70 +270,35 @@ static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
},
};
int rockchip_translate_pull_value(int type, int pull)
{
int i, ret;
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]);
i++) {
if (rockchip_pull_list[type][i] == pull) {
ret = i;
break;
}
}
return ret;
}
static int rockchip_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
struct rockchip_pin_ctrl *ctrl = priv->ctrl;
struct regmap *regmap;
int reg, ret, i, pull_type;
u8 bit;
u32 data;
debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
pin_num, pull);
ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
if (!ctrl->set_pull)
return -ENOTSUPP;
switch (ctrl->type) {
case RK3036:
case RK3128:
data = BIT(bit + 16);
if (pull == PIN_CONFIG_BIAS_DISABLE)
data |= BIT(bit);
ret = regmap_write(regmap, reg, data);
break;
case RV1108:
case RK3188:
case RK3288:
case RK3368:
case RK3399:
/*
* Where need to clean the special mask for
* rockchip_pull_list.
*/
pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK);
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
i++) {
if (rockchip_pull_list[pull_type][i] == pull) {
ret = i;
break;
}
}
if (ret < 0) {
debug("unsupported pull setting %d\n", pull);
return ret;
}
if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) {
regmap_read(regmap, reg, &data);
data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit);
} else {
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
}
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
break;
default:
debug("unsupported pinctrl type\n");
return -EINVAL;
}
return ret;
return ctrl->set_pull(bank, pin_num, pull);
}
static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
@ -430,89 +306,40 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
{
struct rockchip_pinctrl_priv *priv = bank->priv;
struct rockchip_pin_ctrl *ctrl = priv->ctrl;
struct regmap *regmap;
int reg, ret;
u8 bit;
u32 data;
debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
pin_num, enable);
ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
if (ret)
return ret;
if (!ctrl->set_schmitt)
return -ENOTSUPP;
/* enable the write to the equivalent lower bits */
data = BIT(bit + 16) | (enable << bit);
return regmap_write(regmap, reg, data);
}
/*
* Pinconf_ops handling
*/
static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
unsigned int pull)
{
switch (ctrl->type) {
case RK3036:
case RK3128:
return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
pull == PIN_CONFIG_BIAS_DISABLE);
case RV1108:
case RK3188:
case RK3288:
case RK3368:
case RK3399:
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
}
return false;
return ctrl->set_schmitt(bank, pin_num, enable);
}
/* set the pin config settings for a specified pin */
static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
u32 pin, u32 param, u32 arg)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
struct rockchip_pin_ctrl *ctrl = priv->ctrl;
int rc;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
rc = rockchip_set_pull(bank, pin, param);
if (rc)
return rc;
break;
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
case PIN_CONFIG_BIAS_BUS_HOLD:
if (!rockchip_pinconf_pull_valid(ctrl, param))
return -ENOTSUPP;
if (!arg)
return -EINVAL;
rc = rockchip_set_pull(bank, pin, param);
if (rc)
return rc;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (!ctrl->drv_calc_reg)
return -ENOTSUPP;
rc = rockchip_set_drive_perpin(bank, pin, arg);
if (rc < 0)
return rc;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (!ctrl->schmitt_calc_reg)
return -ENOTSUPP;
rc = rockchip_set_schmitt(bank, pin, arg);
if (rc < 0)
return rc;
@ -530,9 +357,8 @@ static const struct pinconf_param rockchip_conf_params[] = {
{ "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
{ "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
{ "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
{ "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
};

69
drivers/pinctrl/rockchip/pinctrl-rockchip.h
View File

@ -8,16 +8,6 @@
#include <linux/types.h>
enum rockchip_pinctrl_type {
RV1108,
RK3036,
RK3128,
RK3188,
RK3288,
RK3368,
RK3399,
};
/**
* Encode variants of iomux registers into a type variable
*/
@ -26,7 +16,6 @@ enum rockchip_pinctrl_type {
#define IOMUX_SOURCE_PMU BIT(2)
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_WRITABLE_32BIT BIT(5)
/**
* Defined some common pins constants
@ -50,9 +39,6 @@ struct rockchip_iomux {
int offset;
};
#define DRV_TYPE_IO_MASK GENMASK(31, 16)
#define DRV_TYPE_WRITABLE_32BIT BIT(31)
/**
* enum type index corresponding to rockchip_perpin_drv_list arrays index.
*/
@ -65,9 +51,6 @@ enum rockchip_pin_drv_type {
DRV_TYPE_MAX
};
#define PULL_TYPE_IO_MASK GENMASK(31, 16)
#define PULL_TYPE_WRITABLE_32BIT BIT(31)
/**
* enum type index corresponding to rockchip_pull_list arrays index.
*/
@ -207,32 +190,6 @@ struct rockchip_pin_bank {
}, \
}
#define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \
iom2, iom3, drv0, drv1, drv2, \
drv3, pull0, pull1, pull2, \
pull3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = -1 }, \
{ .type = iom1, .offset = -1 }, \
{ .type = iom2, .offset = -1 }, \
{ .type = iom3, .offset = -1 }, \
}, \
.drv = { \
{ .drv_type = drv0, .offset = -1 }, \
{ .drv_type = drv1, .offset = -1 }, \
{ .drv_type = drv2, .offset = -1 }, \
{ .drv_type = drv3, .offset = -1 }, \
}, \
.pull_type[0] = pull0, \
.pull_type[1] = pull1, \
.pull_type[2] = pull2, \
.pull_type[3] = pull3, \
}
#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
label, iom0, iom1, iom2, \
iom3, drv0, drv1, drv2, \
@ -299,8 +256,6 @@ struct rockchip_pin_ctrl {
struct rockchip_pin_bank *pin_banks;
u32 nr_banks;
u32 nr_pins;
char *label;
enum rockchip_pinctrl_type type;
int grf_mux_offset;
int pmu_mux_offset;
int grf_drv_offset;
@ -310,15 +265,14 @@ struct rockchip_pin_ctrl {
struct rockchip_mux_route_data *iomux_routes;
u32 niomux_routes;
void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
int (*set_mux)(struct rockchip_pin_bank *bank,
int pin, int mux);
int (*set_pull)(struct rockchip_pin_bank *bank,
int pin_num, int pull);
int (*set_drive)(struct rockchip_pin_bank *bank,
int pin_num, int strength);
int (*set_schmitt)(struct rockchip_pin_bank *bank,
int pin_num, int enable);
};
/**
@ -331,5 +285,12 @@ struct rockchip_pinctrl_priv {
extern const struct pinctrl_ops rockchip_pinctrl_ops;
int rockchip_pinctrl_probe(struct udevice *dev);
void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
int *reg, u8 *bit, int *mask);
bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
int mux, u32 *reg, u32 *value);
int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask);
int rockchip_translate_drive_value(int type, int strength);
int rockchip_translate_pull_value(int type, int pull);
#endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */

103
drivers/pinctrl/rockchip/pinctrl-rv1108.c
View File

@ -75,6 +75,33 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
},
};
static int rv1108_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
u32 data;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
? priv->regmap_pmu : priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
data = (mask << (bit + 16));
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RV1108_PULL_PMU_OFFSET 0x10
#define RV1108_PULL_OFFSET 0x110
@ -101,6 +128,34 @@ static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
}
static int rv1108_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct regmap *regmap;
int reg, ret;
u8 bit, type;
u32 data;
if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
return -ENOTSUPP;
rv1108_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
type = bank->pull_type[pin_num / 8];
ret = rockchip_translate_pull_value(type, pull);
if (ret < 0) {
debug("unsupported pull setting %d\n", pull);
return ret;
}
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RV1108_DRV_PMU_OFFSET 0x20
#define RV1108_DRV_GRF_OFFSET 0x210
@ -128,6 +183,30 @@ static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
}
static int rv1108_set_drive(struct rockchip_pin_bank *bank,
int pin_num, int strength)
{
struct regmap *regmap;
int reg, ret;
u32 data;
u8 bit;
int type = bank->drv[pin_num / 8].drv_type;
rv1108_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
ret = rockchip_translate_drive_value(type, strength);
if (ret < 0) {
debug("unsupported driver strength %d\n", strength);
return ret;
}
/* enable the write to the equivalent lower bits */
data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RV1108_SCHMITT_PMU_OFFSET 0x30
#define RV1108_SCHMITT_GRF_OFFSET 0x388
#define RV1108_SCHMITT_BANK_STRIDE 8
@ -158,6 +237,21 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
static int rv1108_set_schmitt(struct rockchip_pin_bank *bank,
int pin_num, int enable)
{
struct regmap *regmap;
int reg;
u8 bit;
u32 data;
rv1108_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
/* enable the write to the equivalent lower bits */
data = BIT(bit + 16) | (enable << bit);
return regmap_write(regmap, reg, data);
}
static struct rockchip_pin_bank rv1108_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
@ -171,15 +265,14 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = {
static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.pin_banks = rv1108_pin_banks,
.nr_banks = ARRAY_SIZE(rv1108_pin_banks),
.label = "RV1108-GPIO",
.type = RV1108,
.grf_mux_offset = 0x10,
.pmu_mux_offset = 0x0,
.iomux_recalced = rv1108_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
.pull_calc_reg = rv1108_calc_pull_reg_and_bit,
.drv_calc_reg = rv1108_calc_drv_reg_and_bit,
.schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
.set_mux = rv1108_set_mux,
.set_pull = rv1108_set_pull,
.set_drive = rv1108_set_drive,
.set_schmitt = rv1108_set_schmitt,
};
static const struct udevice_id rv1108_pinctrl_ids[] = {

4
drivers/ram/rockchip/dmc-rk3368.c
View File

@ -842,7 +842,11 @@ static int setup_sdram(struct udevice *dev)
move_to_access_state(pctl);
/* TODO(prt): could detect rank in training... */
#ifdef CONFIG_TARGET_EVB_PX5
params->chan.rank = 1;
#else
params->chan.rank = 2;
#endif
/* TODO(prt): bus width is not auto-detected (yet)... */
params->chan.bw = 2; /* 32bit wide bus */
params->chan.dbw = params->chan.dbw; /* 32bit wide bus */

12
drivers/ram/rockchip/sdram_rk322x.c
View File

@ -49,7 +49,7 @@ struct rk322x_sdram_params {
struct regmap *map;
};
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_TPL_BUILD
/*
* [7:6] bank(n:n bit bank)
* [5:4] row(13+n)
@ -750,7 +750,7 @@ static int rk322x_dmc_ofdata_to_platdata(struct udevice *dev)
return 0;
}
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_TPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int conv_of_platdata(struct udevice *dev)
@ -778,7 +778,7 @@ static int conv_of_platdata(struct udevice *dev)
static int rk322x_dmc_probe(struct udevice *dev)
{
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_TPL_BUILD
struct rk322x_sdram_params *plat = dev_get_platdata(dev);
int ret;
struct udevice *dev_clk;
@ -786,7 +786,7 @@ static int rk322x_dmc_probe(struct udevice *dev)
struct dram_info *priv = dev_get_priv(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_TPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
ret = conv_of_platdata(dev);
if (ret)
@ -842,12 +842,12 @@ U_BOOT_DRIVER(dmc_rk322x) = {
.id = UCLASS_RAM,
.of_match = rk322x_dmc_ids,
.ops = &rk322x_dmc_ops,
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_TPL_BUILD
.ofdata_to_platdata = rk322x_dmc_ofdata_to_platdata,
#endif
.probe = rk322x_dmc_probe,
.priv_auto_alloc_size = sizeof(struct dram_info),
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_TPL_BUILD
.platdata_auto_alloc_size = sizeof(struct rk322x_sdram_params),
#endif
};

15
drivers/ram/rockchip/sdram_rk3399.c
View File

@ -30,7 +30,8 @@ struct chan_info {
};
struct dram_info {
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
struct chan_info chan[2];
struct clk ddr_clk;
struct rk3399_cru *cru;
@ -55,7 +56,8 @@ struct dram_info {
#define PHY_DRV_ODT_40 0xe
#define PHY_DRV_ODT_34_3 0xf
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
struct rockchip_dmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
@ -1187,7 +1189,8 @@ static int rk3399_dmc_init(struct udevice *dev)
static int rk3399_dmc_probe(struct udevice *dev)
{
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
if (rk3399_dmc_init(dev))
return 0;
#else
@ -1226,12 +1229,14 @@ U_BOOT_DRIVER(dmc_rk3399) = {
.id = UCLASS_RAM,
.of_match = rk3399_dmc_ids,
.ops = &rk3399_dmc_ops,
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
.ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
#endif
.probe = rk3399_dmc_probe,
.priv_auto_alloc_size = sizeof(struct dram_info),
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
.platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
#endif
};

18
drivers/sysreset/Kconfig
View File

@ -13,6 +13,24 @@ config SYSRESET
to effect a reset. The uclass will try all available drivers when
reset_walk() is called.
config SPL_SYSRESET
bool "Enable support for system reset drivers in SPL mode"
depends on SYSRESET && SPL_DM
help
Enable system reset drivers which can be used to reset the CPU or
board. Each driver can provide a reset method which will be called
to effect a reset. The uclass will try all available drivers when
reset_walk() is called.
config TPL_SYSRESET
bool "Enable support for system reset drivers in TPL mode"
depends on SYSRESET && TPL_DM
help
Enable system reset drivers which can be used to reset the CPU or
board. Each driver can provide a reset method which will be called
to effect a reset. The uclass will try all available drivers when
reset_walk() is called.
if SYSRESET
config SYSRESET_GPIO

2
drivers/sysreset/Makefile
View File

@ -2,7 +2,7 @@
#
# (C) Copyright 2016 Cadence Design Systems Inc.
obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset-uclass.o
obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
obj-$(CONFIG_ARCH_STI) += sysreset_sti.o

1
include/configs/evb_px5.h
View File

@ -9,5 +9,6 @@
#include <configs/rk3368_common.h>
#define CONFIG_CONSOLE_SCROLL_LINES 10
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif

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