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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 23:50:26 +09:00
ram: stm32: add second SDRAM bank management
FMC is able to manage 2 SDRAM banks, but the current driver implementation is only able to manage the first SDRAM bank. Even if only bank2 is used, some bank1 registers must be configured. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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f39b90dc8c
commit
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@ -40,12 +40,19 @@ Example:
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pinctrl-names = "default";
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pinctrl-names = "default";
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status = "okay";
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status = "okay";
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mr-nbanks = <1>;
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/* sdram memory configuration from sdram datasheet */
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/* sdram memory configuration from sdram datasheet */
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bank1: bank@0 {
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bank1: bank@0 {
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st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
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st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
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CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
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CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
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st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
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TRCD_18>;
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TRCD_18>;
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};
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};
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}
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/* sdram memory configuration from sdram datasheet */
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bank2: bank@1 {
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st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
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CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
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TRCD_18>;
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};
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}
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@ -117,12 +117,23 @@ struct stm32_sdram_timing {
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u8 twr;
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u8 twr;
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u8 trcd;
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u8 trcd;
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};
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};
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struct stm32_sdram_params {
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enum stm32_fmc_bank {
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struct stm32_fmc_regs *base;
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SDRAM_BANK1,
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u8 no_sdram_banks;
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SDRAM_BANK2,
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MAX_SDRAM_BANK,
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};
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struct bank_params {
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struct stm32_sdram_control *sdram_control;
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struct stm32_sdram_control *sdram_control;
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struct stm32_sdram_timing *sdram_timing;
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struct stm32_sdram_timing *sdram_timing;
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u32 sdram_ref_count;
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u32 sdram_ref_count;
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enum stm32_fmc_bank target_bank;
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};
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struct stm32_sdram_params {
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struct stm32_fmc_regs *base;
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u8 no_sdram_banks;
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struct bank_params bank_params[MAX_SDRAM_BANK];
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};
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};
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#define SDRAM_MODE_BL_SHIFT 0
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#define SDRAM_MODE_BL_SHIFT 0
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@ -132,96 +143,154 @@ struct stm32_sdram_params {
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int stm32_sdram_init(struct udevice *dev)
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int stm32_sdram_init(struct udevice *dev)
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{
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{
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struct stm32_sdram_params *params = dev_get_platdata(dev);
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struct stm32_sdram_params *params = dev_get_platdata(dev);
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struct stm32_sdram_control *control;
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struct stm32_sdram_timing *timing;
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struct stm32_fmc_regs *regs = params->base;
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struct stm32_fmc_regs *regs = params->base;
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struct stm32_sdram_control *control = params->sdram_control;
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enum stm32_fmc_bank target_bank;
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struct stm32_sdram_timing *timing = params->sdram_timing;
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u32 ctb; /* SDCMR register: Command Target Bank */
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u32 ref_count;
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u8 i;
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writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
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for (i = 0; i < params->no_sdram_banks; i++) {
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| control->cas_latency << FMC_SDCR_CAS_SHIFT
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control = params->bank_params[i].sdram_control;
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| control->no_banks << FMC_SDCR_NB_SHIFT
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timing = params->bank_params[i].sdram_timing;
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| control->memory_width << FMC_SDCR_MWID_SHIFT
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target_bank = params->bank_params[i].target_bank;
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| control->no_rows << FMC_SDCR_NR_SHIFT
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ref_count = params->bank_params[i].sdram_ref_count;
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| control->no_columns << FMC_SDCR_NC_SHIFT
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| control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
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| control->rd_burst << FMC_SDCR_RBURST_SHIFT,
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®s->sdcr1);
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writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
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writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
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| timing->trp << FMC_SDTR_TRP_SHIFT
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| control->cas_latency << FMC_SDCR_CAS_SHIFT
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| timing->twr << FMC_SDTR_TWR_SHIFT
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| control->no_banks << FMC_SDCR_NB_SHIFT
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| timing->trc << FMC_SDTR_TRC_SHIFT
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| control->memory_width << FMC_SDCR_MWID_SHIFT
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| timing->tras << FMC_SDTR_TRAS_SHIFT
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| control->no_rows << FMC_SDCR_NR_SHIFT
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| timing->txsr << FMC_SDTR_TXSR_SHIFT
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| control->no_columns << FMC_SDCR_NC_SHIFT
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| timing->tmrd << FMC_SDTR_TMRD_SHIFT,
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| control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
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®s->sdtr1);
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| control->rd_burst << FMC_SDCR_RBURST_SHIFT,
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®s->sdcr1);
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writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
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if (target_bank == SDRAM_BANK2)
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®s->sdcmr);
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writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
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udelay(200); /* 200 us delay, page 10, "Power-Up" */
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| control->no_banks << FMC_SDCR_NB_SHIFT
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FMC_BUSY_WAIT(regs);
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| control->memory_width << FMC_SDCR_MWID_SHIFT
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| control->no_rows << FMC_SDCR_NR_SHIFT
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| control->no_columns << FMC_SDCR_NC_SHIFT,
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®s->sdcr2);
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writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
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writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
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®s->sdcmr);
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| timing->trp << FMC_SDTR_TRP_SHIFT
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udelay(100);
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| timing->twr << FMC_SDTR_TWR_SHIFT
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FMC_BUSY_WAIT(regs);
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| timing->trc << FMC_SDTR_TRC_SHIFT
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| timing->tras << FMC_SDTR_TRAS_SHIFT
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| timing->txsr << FMC_SDTR_TXSR_SHIFT
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| timing->tmrd << FMC_SDTR_TMRD_SHIFT,
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®s->sdtr1);
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writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
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if (target_bank == SDRAM_BANK2)
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| 7 << FMC_SDCMR_NRFS_SHIFT), ®s->sdcmr);
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writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
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udelay(100);
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| timing->trp << FMC_SDTR_TRP_SHIFT
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FMC_BUSY_WAIT(regs);
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| timing->twr << FMC_SDTR_TWR_SHIFT
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| timing->trc << FMC_SDTR_TRC_SHIFT
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| timing->tras << FMC_SDTR_TRAS_SHIFT
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| timing->txsr << FMC_SDTR_TXSR_SHIFT
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| timing->tmrd << FMC_SDTR_TMRD_SHIFT,
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®s->sdtr2);
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if (target_bank == SDRAM_BANK1)
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ctb = FMC_SDCMR_BANK_1;
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else
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ctb = FMC_SDCMR_BANK_2;
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writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
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writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr);
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| control->cas_latency << SDRAM_MODE_CAS_SHIFT)
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udelay(200); /* 200 us delay, page 10, "Power-Up" */
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<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
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FMC_BUSY_WAIT(regs);
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®s->sdcmr);
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udelay(100);
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FMC_BUSY_WAIT(regs);
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writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
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writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr);
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®s->sdcmr);
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udelay(100);
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FMC_BUSY_WAIT(regs);
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FMC_BUSY_WAIT(regs);
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/* Refresh timer */
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writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT),
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writel((params->sdram_ref_count) << 1, ®s->sdrtr);
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®s->sdcmr);
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udelay(100);
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FMC_BUSY_WAIT(regs);
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writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
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| control->cas_latency << SDRAM_MODE_CAS_SHIFT)
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<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
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®s->sdcmr);
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udelay(100);
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FMC_BUSY_WAIT(regs);
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writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr);
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FMC_BUSY_WAIT(regs);
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/* Refresh timer */
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writel(ref_count << 1, ®s->sdrtr);
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}
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return 0;
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return 0;
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}
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}
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static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
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static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
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{
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{
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ofnode bank_node;
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struct stm32_sdram_params *params = dev_get_platdata(dev);
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struct stm32_sdram_params *params = dev_get_platdata(dev);
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struct bank_params *bank_params;
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params->no_sdram_banks = dev_read_u32_default(dev, "mr-nbanks", 1);
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ofnode bank_node;
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debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
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char *bank_name;
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u8 bank = 0;
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dev_for_each_subnode(bank_node, dev) {
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dev_for_each_subnode(bank_node, dev) {
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params->sdram_control = (struct stm32_sdram_control *)
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/* extract the bank index from DT */
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ofnode_read_u8_array_ptr(bank_node,
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bank_name = (char *)ofnode_get_name(bank_node);
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"st,sdram-control",
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strsep(&bank_name, "@");
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sizeof(struct stm32_sdram_control));
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if (!bank_name) {
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error("missing sdram bank index");
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if (!params->sdram_control) {
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error("st,sdram-control not found for device: %s",
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dev->name);
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return -EINVAL;
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return -EINVAL;
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}
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}
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params->sdram_timing = (struct stm32_sdram_timing *)
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bank_params = ¶ms->bank_params[bank];
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ofnode_read_u8_array_ptr(bank_node,
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strict_strtoul(bank_name, 10,
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"st,sdram-timing",
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(long unsigned int *)&bank_params->target_bank);
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sizeof(struct stm32_sdram_timing));
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if (!params->sdram_timing) {
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if (bank_params->target_bank >= MAX_SDRAM_BANK) {
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error("st,sdram-timing not found for device: %s",
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error("Found bank %d , but only bank 0 and 1 are supported",
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dev->name);
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bank_params->target_bank);
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return -EINVAL;
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return -EINVAL;
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}
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}
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params->sdram_ref_count = ofnode_read_u32_default(bank_node,
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debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
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params->bank_params[bank].sdram_control =
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(struct stm32_sdram_control *)
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ofnode_read_u8_array_ptr(bank_node,
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"st,sdram-control",
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sizeof(struct stm32_sdram_control));
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if (!params->bank_params[bank].sdram_control) {
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error("st,sdram-control not found for %s",
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ofnode_get_name(bank_node));
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return -EINVAL;
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}
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params->bank_params[bank].sdram_timing =
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(struct stm32_sdram_timing *)
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ofnode_read_u8_array_ptr(bank_node,
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"st,sdram-timing",
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sizeof(struct stm32_sdram_timing));
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if (!params->bank_params[bank].sdram_timing) {
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error("st,sdram-timing not found for %s",
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ofnode_get_name(bank_node));
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return -EINVAL;
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}
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bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
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"st,sdram-refcount", 8196);
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"st,sdram-refcount", 8196);
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bank++;
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}
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}
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params->no_sdram_banks = bank;
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debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
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return 0;
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return 0;
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}
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}
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