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omap: am33xx: accomodate input clocks other than 24 Mhz

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The PLL setup values currently assume a 24 Mhz input clock.

This patch uses V_OSCK from the board config file to support boards
with different input clock rates.

Signed-off-by: Steve Sakoman <steve@sakoman.com>
This commit is contained in:
Steve Sakoman 2012-05-30 07:46:00 +00:00 committed by Albert ARIBAUD
parent ad0878a749
commit f2b37a6533
1 changed files with 5 additions and 5 deletions
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10
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
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@ -19,16 +19,16 @@
#ifndef _CLOCKS_AM33XX_H_ #ifndef _CLOCKS_AM33XX_H_
#define _CLOCKS_AM33XX_H_ #define _CLOCKS_AM33XX_H_
#define OSC 24 #define OSC (V_OSCK/1000000)
/* MAIN PLL Fdll = 550 MHZ, */ /* MAIN PLL Fdll = 550 MHZ, */
#define MPUPLL_M 550 #define MPUPLL_M 550
#define MPUPLL_N 23 #define MPUPLL_N (OSC-1)
#define MPUPLL_M2 1 #define MPUPLL_M2 1
/* Core PLL Fdll = 1 GHZ, */ /* Core PLL Fdll = 1 GHZ, */
#define COREPLL_M 1000 #define COREPLL_M 1000
#define COREPLL_N 23 #define COREPLL_N (OSC-1)
#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
@ -40,13 +40,13 @@
* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
*/ */
#define PERPLL_M 960 #define PERPLL_M 960
#define PERPLL_N 23 #define PERPLL_N (OSC-1)
#define PERPLL_M2 5 #define PERPLL_M2 5
/* DDR Freq is 266 MHZ for now */ /* DDR Freq is 266 MHZ for now */
/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
#define DDRPLL_M 266 #define DDRPLL_M 266
#define DDRPLL_N 23 #define DDRPLL_N (OSC-1)
#define DDRPLL_M2 1 #define DDRPLL_M2 1
extern void pll_init(void); extern void pll_init(void);